DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD4564323
64M-bit Synchronous DRAM
4-bank, LVTTL
for Rev. E
Description
The
µ
PD4564323 is a high-speed 67,108,864-bit synchronous dynamic random-access memory, organized as
524,288 words
×
32 bits
×
4 banks.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 86-pin TSOP (II).
Features
•
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
•
Pulsed interface
•
Possible to assert random column address in every cycle
•
Quad internal banks controlled by BA0 and BA1 (Bank Select)
• ×32
organization
•
Byte control by DQM0, DQM1, DQM2 and DQM3
•
Programmable Wrap sequence (Sequential / Interleave)
•
Programmable burst length (1, 2, 4, 8 and full page)
•
Programmable /CAS latency (2 and 3)
•
Automatic precharge and controlled precharge
•
CBR (Auto) refresh and self refresh
•
Single 3.3 V
±
0.3 V power supply
•
LVTTL compatible inputs and outputs
•
4,096 refresh cycles / 64 ms
•
Burst termination by Burst stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
M14376EJ2V0DS00 (2nd edition)
Date Published December 1999 NS CP (K)
Printed in Japan
The mark
•
shows major revised points.
©
1999
µ
PD4564323 for Rev. E
5
Ordering Information
Part number
Organization
(word
×
bit
×
bank)
512K
×
32
×
4
Clock frequency
MHz (MAX.)
166
143
125
100
100
Package
86-pin Plastic TSOP (II)
(10.16 mm (400))
µ
PD4564323G5-A60-9JH
µ
PD4564323G5-A70-9JH
µ
PD4564323G5-A80-9JH
µ
PD4564323G5-A10-9JH
µ
PD4564323G5-A10B-9JH
2
Data Sheet M14376EJ2V0DS00
µ
PD4564323 for Rev. E
5
Part Number
µ
PD4564323G5 - A60
NEC Memory
Synchronous
DRAM
Memory Density
64 : 64M bits
Minimum Cycle Time
60 : 6 ns (166MHz)
70 : 7 ns (143MHz)
80 : 8 ns (125MHz)
10 : 10 ns (100MHz)
10B : 10 ns (100MHz)
Organization
32 : x32
Number of Banks
& Interface
3 : 4Bank, LVTTL
Low Voltage
A : 3.3
±
0.3 V
Package
G5 : TSOP(II)
Data Sheet M14376EJ2V0DS00
3
µ
PD4564323 for Rev. E
Pin Configuration
/xxx indicates active low signal.
[
µ
PD4564323]
86-pin Plastic TSOP (II) (10.16 mm (400))
512K words
×
32 bits
×
4 banks
V
CC
DQ0
V
CC
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
CC
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
CC
DQM0
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10(AP)
A0
A1
A2
DQM2
V
CC
NC
DQ16
V
SS
Q
DQ17
DQ18
V
CC
Q
DQ19
DQ20
V
SS
Q
DQ21
DQ22
V
CC
Q
DQ23
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
CC
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
CC
Q
DQ8
NC
V
SS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
V
SS
NC
DQ31
V
CC
Q
DQ30
DQ29
V
SS
Q
DQ28
DQ27
V
CC
Q
DQ26
DQ25
V
SS
Q
DQ24
V
SS
A0 to A10
: Address inputs
BA0, BA1
: Bank select
DQ0 to DQ31 : Data inputs / outputs
CLK
: Clock input
CKE
: Clock enable
/CS
: Chip select
/RAS
: Row address strobe
/CAS
: Column address strobe
/WE
: Write enable
DQM0 to DQM3 : DQ mask enable
V
CC
: Supply voltage
V
SS
: Ground
V
CC
Q
: Supply voltage for DQ
V
SS
Q
: Ground for DQ
NC
: No connection
4
Note
Note
A0 to A10 : Row address inputs
A0 to A7 : Column address inputs
Data Sheet M14376EJ2V0DS00
µ
PD4564323 for Rev. E
Block Diagram
CLK
CKE
Clock
Generator
Bank D
Bank C
Bank B
Address
Row Decoder
Mode
Register
Row
Address
Buffer
&
Refresh
Counter
Bank A
Sense Amplifier
Command Decoder
Control Logic
/CS
/RAS
/CAS
/WE
Data Control Circuit
Input & Output
Buffer
Latch Circuit
Column
Address
Buffer
&
Burst
Counter
Column Decoder &
Latch Circuit
DQM
DQ
Data Sheet M14376EJ2V0DS00
5
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