K4G163222A
256K x 32Bit x 2 Banks Synchronous Graphic RAM
FEATURES
•
•
•
•
3.3V power supply
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-. CAS Latency (2, 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
DQM 0-3 for byte masking
Auto & self refresh
32ms refresh period (2K cycle)
100 Pin PQFP, TQFP (14 x 20 mm)
CMOS SGRAM
GENERAL DESCRIPTION
The K4G163222A is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 262,144 words by 32 bits,
fabricated with SAMSUNG′s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length, and programmable latencies allows the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
Write per bit and 8 columns block write improves performance in
graphics systems.
•
•
•
•
•
•
ORDERING INFORMATION
Part NO.
K4G163222A-PC/L50
K4G163222A-PC/L55
K4G163222A-PC/L60
K4G163222A-PC/L70
K4G163222A-PC/L80
K4G163222A-QC/L50
K4G163222A-QC/L55
K4G163222A-QC/L60
K4G163222A-QC/L70
K4G163222A-QC/L80
Max Freq.
200MHz
183MHz
166MHz
143MHz
125MHz
200MHz
183MHz
166MHz
143MHz
125MHz
Interface
Package
Graphics Features
• SMRS cycle.
-. Load mask register
-. Load color register
• Write Per Bit(Old Mask)
• Block Write(8 Columns)
LVTTL
100 PQFP
LVTTL
100 TQFP
FUNCTIONAL BLOCK DIAGRAM
DQMi
BLOCK
WRITE
CONTROL
LOGIC
CLK
CKE
CS
MASK
WRITE
MASK
REGISTER
COLOR
REGISTER
INPUT BUFFER
CONTROL
LOGIC
MUX
•
COLUMN
MASK
DQMi
DQi
(i=0~31)
TIMING REGISTER
SENSE
AMPLIFIER
RAS
CAS
WE
DSF
DQMi
•
256Kx32
CELL
ARRAY
256Kx32
CELL
ARRAY
ROW DECORDER
BANK SELECTION
•
SERIAL
COUNTER
COLUMN ADDRESS
BUFFER
ROW ADDRESS
BUFFER
REFRESH
COUNTER
ADDRESS REGISTER
CLOCK ADDRESS(A
0
~A
10
)
* Samsung Electronics reserves the right to
change products or specification without
notice.
OUTPUT BUFFER
LATENCY &
BURST LENGTH
PROGRAMING
REGISTER
COLUMN
DECORDER
K4G163222A
PIN CONFIGURATION
(TOP VIEW)
DQ28
VDDQ
DQ27
DQ26
V
SSQ
DQ25
DQ24
V
DDQ
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
DDQ
V
SS
V
DD
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
DDQ
NC
DQM3
DQM1
CLK
CKE
DSF
N.C
A
9 /AP
CMOS SGRAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQ29
V
SSQ
DQ30
DQ31
V
SS
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
V
DD
DQ0
DQ1
V
SSQ
DQ2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100 Pin QFP
Forward Type
20 x 14 mm
2
0.65mm pin Pitch
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
A
7
A
6
A
5
A
4
V
SS
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
V
DD
A
3
A
2
A
1
A
0
*PQFP (Height = 3.0mmMAX)
TQFP (Height = 1.2mmMAX)
PIN CONFIGURATION DESCRIPTION
Pin
CLK
CS
Name
System Clock
Chip Select
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQMi
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / Column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
9
, Column address : CA
0
~ CA
7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and Row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.(Byte Masking)
Data inputs/outputs are multiplexed on the same pins.
Enables write per bit, block write and special mode register set.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
CKE
Clock Enable
A
0
~ A
9
BA(A
10
)
RAS
CAS
WE
DQMi
DQi
DSF
V
DD
/V
SS
V
DDQ
/V
SSQ
N.C
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Define Special Function
Power Supply /Ground
Data Output Power /Ground
No Connection
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
DQ16
DQ17
V
SSQ
DQ18
DQ19
V
DDQ
V
DD
V
SS
DQ20
DQ21
V
SSQ
DQ22
DQ23
V
DDQ
DQM0
DQM2
WE
CAS
RAS
CS
BA(A
10
)
A
8
K4G163222A
ABSOLUTE MAXIMUM RATINGS
(Voltage referenced to V
SS
)
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0
~
4.6
-1.0
~
4.6
-55 ~ +150
1
50
CMOS SGRAM
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V)
Parameter
Supply voltage
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current
Output leakage current
Output Loading Condition
Symbol
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
LI
I
LO
Min
3.0
2.0
-0.3
2.4
-
-10
-10
Typ
3.3
3.0
0
-
-
-
-
Max
3.6
V
DDQ
+0.3
0.8
-
0.4
10
10
see figure 1
Unit
V
V
V
V
V
uA
uA
Note
5
1
2
I
OH
= -2mA
I
OL
= 2mA
3
4
Note :
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V
≤
V
OUT
≤
V
DD.
5. The VDD condition of K4G163222A-50/55/60 is 3.135V~3.6V.
CAPACITANCE
(V
DD
/V
DDQ
= 3.3V, T
A
= 23°C, f = 1MHz)
Pin
Clock
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
-
-
-
-
Max
4.0
4.0
4.0
5.0
Unit
pF
pF
pF
pF
RAS, CAS, WE, CS, CKE, DQM
i
,DSF
Address
DQ
i
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Decoupling Capacitance between V
DD
and V
SS
Decoupling Capacitance between V
DDQ
and V
SSQ
Symbol
C
DC1
C
DC2
Value
0.1 + 0.01
0.1 + 0.01
Unit
uF
uF
Note :
1. V
DD
and V
DDQ
pins are separated each other.
All V
DD
pins are connected in chip. All V
DDQ
pins are connected in chip.
2. V
SS
and V
SSQ
pins are separated each other
All V
SS
pins are connected in chip. All V
SSQ
pins are connected in chip.
K4G163222A
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70°C, V
IH(min)
/V
IL(max)
=2.0V/0.8V)
Parameter
Operating Current
(One Bank Active)
Symbol
Test Condition
CAS
Latency -50
3
2
200
-
CMOS SGRAM
Speed
-55
190
-
-60
180
-
2
2
30
-70
160
-
-80
150
Unit Note
I
CC1
Burst Length =1
t
RC
≥
t
RC
(min), t
CC
≥
t
CC
(min), I
o
= 0mA
CKE
≤
V
IL
(max), t
CC
= 15ns
CKE
&
CLK
≤
V
IL
(max), t
CC
=
∞
mA
150
mA
2
Precharge Standby Current I
CC2
P
in power-down mode
I
CC2
PS
I
CC2
N
Precharge Standby Current
in non power-down mode
I
CC2
NS
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
Operating Current
(Burst Mode)
Refresh Current
I
CC3
P
I
CC3
PS
I
CC3
N
I
CC3
NS
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
CKE
≤
V
IL
(max), t
CC
= 15ns
CKE
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
o
= 0 mA, Page Burst
All bank Activated, t
CCD
= t
CCD
(min)
t
RC
≥
t
RC
(min)
CKE
≤
0.2V
t
CC
≥
t
CC
(min), I
o
=0mA, t
BWC
(min)
3
2
3
2
290
-
200
-
270
-
190
-
mA
15
3
3
50
mA
30
260
-
180
-
2
450
230
-
160
-
200
160
150
150
mA
uA
170
150
mA
4
5
mA
3
mA
I
CC4
mA
2
I
CC5
Self Refresh Current
Operating Current
(One Bank Block Write)
I
CC6
I
CC7
230
210
200
Note :
1. Unless otherwise notes, Input level is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ
) in LVTTL.
2. Measured with outputs open. Addresses are changed only one time during tcc(min).
3. Refresh period is 32ms. Addresses are changed only one time during tcc(min).
4. K4G163222A-C*
5. K4G163222A-L* : Low Power version
K4G163222A
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V±0.3V, T
A
= 0 to 70°C)
Parameter
Input levels (V
ih
/V
il
)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
3.3V
Value
2.4 / 0.4
1.4
CMOS SGRAM
Unit
V
V
ns
V
t
r
/
t
f
=1 / 1
1.4
See Fig. 2
V
tt
= 1.4V
1200Ω
Output
870Ω
•
(Fig. 1) DC Output Load Circuit
Note :
1. The VDD condition of K4G163222A-50/55/60 is 3.135V~3.6V.
•
•
30pF
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
Output
Z0=50Ω
•
50Ω
30pF
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
CAS Latency
CLK cycle time
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to new col.address delay
Last data in to burst stop
Col. address to col. address delay
Block Write data-in to PRE command
Block write cycle time
Mode Register Set cycle time
Number of valid output data
Symbol
CL
t
CC(min)
t
RRD(min)
t
RCD(min)
t
RP(min)
t
RAS(min)
t
RAS(max)
t
RC
(
min
)
t
RDL(min)
t
CDL(min)
t
BDL(min)
t
CCD(min)
t
BPL(min)
t
BWC(min)
t
MRS(min)
CAS Latency=3
CAS Latency=2
12
-
10
-
4
4
8
-
-
-
3
3
7
-
-
-
3
3
7
100
10
2
1
1
1
2
1
1
2
1
-
10
-
9
7
3
5
Version
-50
2
-
3
5.5
-55
2
-
3
6
2
-
-
-
3
3
7
-
-
-
3
3
6
2
2
5
-60
2
-
3
7
-70
2
-
3
8
-80
2
10
Unit
CLK
ns
CLK
CLK
CLK
CLK
us
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
ea
4
3
1
2,
5
2
2
1
1
1
1
Note
Note :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following ns-unit based AC table.
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