Device
Engineering
Incorporated
385 E. Alamo Dr.
Chandler, AZ 85225
Phone: (480) 303-0822
Fax: (480) 303-0824
E-mail: admin@deiaz.com
DEI1166
OCTAL GND/OPEN INPUT,
PARALLEL OUTPUT INTERFACE IC
FEATURES
•
Eight GND/OPEN discrete inputs
o
Meet electrical requirements for ABD0100 GND/OPEN discrete input.
o
Hysteresis provides noise immunity.
o
Internal pull up resistor with 1mA source current to prevent dry relay contacts.
o
Internal isolation diode
o
Inputs protected from Lightning Induced Transients per DO160D, Section 22, Cat A3 and B3.
3.3V or 5V TTL/CMOS compatible digital IO
o
8 tri-state outputs
o
/CS & /OE control inputs
Logic Supply:
3.3V or 5V
Analog Supply:
5V to 18V
24L TSSOP package
•
•
•
•
PIN ASSIGNMENTS
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DIN8
NC
NC
/CS
/OE
1
2
3
4
5
6
7
8
9
10
11
12
24
DO1
DO2
GND
DO3
DO4
VCC
DO5
DO6
DO7
DO8
GND
VDD
DEI1166
23
22
21
20
19
18
17
16
15
14
13
Figure 1 DEI1166 Pin Assignment (24 Lead TSSOP)
©2005 Device Engineering Inc
Page 1 of 9
DS-MW-01166-01 Rev C
02/28/2005
Table 1 Pin Descriptions
Pins
8-1
9-10
11
12
13
14
19
22
15,16,17,18,20,21,23,24
Name
DIN[8:1]
NC
/CS
/OE
VDD
GND
VCC
GND
DO[8:1]
Description
Discrete Inputs. Eight Ground/Open format discrete signals. These have an
internal pull-up to VDD. The threshold and hysteresis characteristics are
determined by the applied VDD voltage.
Not Connected.
Chip Select Logic Input. Low input selects the device.
Output Enable Logic Input. Low input when /CS is low will enable the tri-
state outputs.
Analog Supply. +5 to +18V
Analog Ground.
Logic Supply. +3.3V or +5V
Logic Ground.
Logic Outputs. Eight tri-state data outputs.
FUNCTIONAL DESCRIPTION
The DEI1166 is an eight-channel parallel-output discrete-to-digital interface BICMOS device. It senses eight Ground/Open
discrete signals of the type commonly found in avionic systems. The data is read from the device via a parallel 3-state output.
O E
CE
V
DD
D IN 1
VCC
2K
12K
2K
T H R E SH O LD
AND
H Y S T E R S IS
+
-
DO1
D IN 2
12K
2K
+
TH R E S H O L D
AND
H Y S T E R S IS
-
-
DO2
D IN 3
12K
+
2K
T H R ES H O LD
AN D
H Y S TE R S I S
DO 3
D IN 4
12 K
2K
T H R ES H O LD
AN D
H Y S TE R S I S
+
-
DO4
D IN 5
12K
2K
+
12 K
2K
T H R ES H O LD
AN D
H Y S TE R S I S
-
-
DO5
D IN 6
+
TH R E S H O L D
AND
H Y S T E R S IS
DO 6
D IN 7
12 K
T H R ES H O LD
AN D
H Y S TE R S I S
+
-
-
DO 7
2K
D IN 8
12K
TH R ES H OL D
AN D
H Y S T E R S IS
+
DO 8
G ND
Figure 2 DEI1166 Function Diagram
©2005 Device Engineering Inc
Page 2 of 9
DS-MW-01166-01 Rev C
02/28/2005
Typical DINn Threshold Voltage & Hystersis
18
16
14
12
10
8
6
4
2
0
0
5
10
15
20
Vdd Supply Voltage (V)
DIN Threshold Voltage (V)
Vth+
Vth-
Figure 3 DIN Threshold vs Vdd
Table 2 Truth Table
/CE
L
L
H
X
/OE
L
L
X
H
DIN[8:1]
Open
Ground
X
X
DO[8:1]
L
H
High Z
High Z
DIN[8:1] INPUT STRUCTURE
Refer to Figure 2. Each DINn signal is conditioned by the resistor / diode network and presented to the comparator IN+. The
reference and hysteresis voltage is developed at the comparator IN-. Some notable features are:
•
•
When Vdd is +15V, the circuit shall source >1mA to a grounded input. This current will prevent a “dry” relay
contact.
The input threshold voltage and hysteresis varies with the Vdd supply.
o
For Vdd of +5V, VILmax = 3.5V, VIHmin = 4.8V
o
For Vdd of +14V, VILmax = 11.8V, VIHmin = 13.5V
o
Hysteresis is approximately as shown in Figure 3.
The inputs can withstand continuous input voltages of 40V maximum. The isolation diode breakdown voltage is
greater than 50V. The 12K Ohm input resistor is designed to limit diode breakdown current to safe levels during
transient events.
•
The input thresholds vary with Vdd supply voltages and can be approximated as follows:
For Vdd = 5V to 18V
Vlh_max = 0.98*Vdd – 0.65 V
Vhl_min = 0.95*Vdd – 0.8V
©2005 Device Engineering Inc
Page 3 of 9
DS-MW-01166-01 Rev C
02/28/2005
TIMING DIAGRAMS
Figure 4 Input to Output Delay
3V
3V
V
IN
= V
DD
V
IN
= V
SS
OE or CE
1.5
R
L
= 5K Ohm to V
DD
C
L
= 30pF
1.5V
0
R
L
= 5K Ohm to V
SS
C
L
= 30pF
0
t
ZL
t
LZ
HIGH-Z
0.2
t
ZH
HI
t
HZ
0.2
HIGH-Z
OUTPUT
LO
0.2
HIGH Z
0.2
HIGH Z
Figure 5 Chip Select or Output Enable to Output Delay
©2005 Device Engineering Inc
Page 4 of 9
DS-MW-01166-01 Rev C
02/28/2005
LIGHTNING PROTECTION
DINn inputs are designed to survive lightning induced transients as defined by RTCA DO160D, Section 22, Cat A3 and B3,
Waveforms 3, 4, and 5A, Level 3. See waveforms below.
V/I
25% to 75%
of Largest Peak
50%
V
Peak
T1 = 6.4uS
T2 = 70uS
0
t
50%
F = 1MHZ and 10MHZ
Figure 6 Voltage / Current Waveform 3
0
T1
T2
t
Figure 7 Voltage Waveform 4
V/I
Peak
Waveform Source Impedance characteristics:
•
Waveform 3 Voc/Isc = 600V / 24A => 25 Ohms
•
Waveform 4 Voc/Isc = 300 V / 60 A => 5 Ohms
•
Waveform 5A Voc / Isc = 300V / 300A => 1 Ohm
50%
T1=40uS
T2=120uS
0
T1
T2
t
Figure 8 Current/Voltage Waveform 5A
©2005 Device Engineering Inc
Page 5 of 9
DS-MW-01166-01 Rev C
02/28/2005
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