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HY27US16561A-FPEB

Description
Flash, 16MX16, 30ns, PBGA63, 9 X 11 MM, 1 MM HEIGHT, LEAD FREE, FBGA-63
Categorystorage    storage   
File Size423KB,47 Pages
ManufacturerSK Hynix
Websitehttp://www.hynix.com/eng/
Environmental Compliance  
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HY27US16561A-FPEB Overview

Flash, 16MX16, 30ns, PBGA63, 9 X 11 MM, 1 MM HEIGHT, LEAD FREE, FBGA-63

HY27US16561A-FPEB Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSK Hynix
Parts packaging codeBGA
package instructionVFBGA, BGA63,10X12,32
Contacts63
Reach Compliance Codecompliant
ECCN code3A991.B.1.A
Maximum access time30 ns
command user interfaceYES
Data pollingNO
JESD-30 codeR-PBGA-B63
JESD-609 codee1
length11 mm
memory density268435456 bit
Memory IC TypeFLASH
memory width16
Number of functions1
Number of departments/size2K
Number of terminals63
word count16777216 words
character code16000000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-25 °C
organize16MX16
Package body materialPLASTIC/EPOXY
encapsulated codeVFBGA
Encapsulate equivalent codeBGA63,10X12,32
Package shapeRECTANGULAR
Package formGRID ARRAY, VERY THIN PROFILE, FINE PITCH
page size256 words
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
power supply3/3.3 V
Programming voltage3.3 V
Certification statusNot Qualified
ready/busyYES
Maximum seat height1 mm
Department size8K
Maximum standby current0.00005 A
Maximum slew rate0.02 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2.7 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal surfaceTin/Silver/Copper (Sn/Ag/Cu)
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature20
switch bitNO
typeSLC NAND TYPE
width9 mm
HY27US(08/16)561A Series
HY27SS(08/16)561A Series
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash
Document Title
256Mbit (32Mx8bit / 16Mx16bit) NAND Flash Memory
Revision History
Revision
No.
0.0
Initial Draft.
1) Change AC Parameter
tCRY(1.8V)
Before
50+tr(R/B#)
60+tr(R/B#)
History
Draft Date
Apr. 04. 2005
Remark
Preliminary
0.1
After
Jul. 07. 2005
Preliminary
2) Change 256Mb Package Type.
- WSOP package is changed to USOP package.
- Figure & dimension are changed.
1)
Correct the test Conditions (DC Characteristics table)
Test Conditions (
I
CC1)
Before
Test Conditions (
I
LI,
I
LO
)
VIN=VOUT=0 to 3.6V
t
RC
=50ns,
CE#=
V
IL
,
I
OUT
=0mA
t
RC
(1.8V=60ns,
3.3V=50ns)
CE#=
V
IL
,
I
OUT
=0mA
After
VIN=VOUT=0 to Vcc (max)
0.2
2)
Change AC Conditions table
3)
Add tWW parameter ( tWW = 100ns, min)
- Texts & Figures are added.
- tWW is added in AC timing characteristics table.
4) Edit Copy Back Program operation step
5) Edit System Interface Using CE don’t care Figures.
6) Correct Address Cycle Map.
7) Change NOP (table 11)
Main Array
Before
After
1
2
Aug. 08. 2005
Preliminary
Spare Array
2
3
Rev 0.5 / Jun. 2006
1
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