K4S511533C-YL/N/P
CMOS SDRAM
32Mx16
Mobile SDRAM
54CSP 2/CS
(VDD/VDDQ 3.0V/3.0V or 3.3V/3.3V)
Revision 1.2
December 2002
Rev. 1.2 Dec. 2002
K4S511533C-YL/N/P
8M x 16Bit x 4 Banks Mobile SDRAM
FEATURES
• 3.0V power supply
• LVCMOS compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (1 & 2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• DQM for masking
• Auto & self refresh
• 64ms refresh period (8K cycle)
• 2 /CS Support.
• Commercial Temperature Operation (-25°C ~ 70°C).
Extended Temperature Operation (-25°C ~ 85°C).
Industrial Temperature Operation (-40°C ~ 85°C).
• 54balls DDP CSP
K4S511533C-YL/N/P1H
K4S511533C-YL/N/P1L
CMOS SDRAM
GENERAL DESCRIPTION
The K4S511533C is 536,870,912 bits synchronous high data
rate Dynamic RAM organized as 4 x 8,388,608 words by 16bits,
fabricated with SAMSUNG's high performance CMOS technology.
Synchronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system
applications.
ORDERING INFORMATION
Part No.
K4S511533C-YL/N/P80
Max Freq.
125MHz(CL=3)
100MHz(CL=2)
100MHz(CL=2)
100MHz(CL=3)
*1
LVCMOS
54 CSP
Interface Package
- YN : Low Power, Operating Temp : -25°C ~ 85°C.
- YL : Low Power, Operating Temp : -25°C ~ 70°C.
- YP : Low Power, Operating Temp : -40°C ~ 85°C.
Note :
1. In case of 33MHz Frequency, CL1 can be supported.
FUNCTIONAL BLOCK DIAGRAM
CLK, /CAS, /RAS,
/WE, DQM, CKE
/CS1
16Mx16
16Mx16
/CS0
DQ0~DQ15
A0~A12, BA0, BA1
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.2 Dec. 2002
K4S511533C-YL/N/P
Package Dimension and Pin Configuration
< Bottom View
*1
>
E
1
CMOS SDRAM
< Top View
*2
>
54Ball(6x9) CSP
1
2
DQ15
DQ13
DQ11
DQ9
CS1
CLK
A11
A7
A5
3
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
SS
CKE
A9
A6
A4
7
V
DDQ
V
SSQ
V
DDQ
V
SSQ
V
DD
CAS
BA0
A0
A3
8
DQ0
DQ2
DQ4
DQ6
LDQM
RAS
BA1
A1
A2
9
V
DD
DQ1
DQ3
DQ5
DQ7
WE
CS0
A10
V
DD
A
e
9
A
B
C
D
D
1
E
F
8
7
6
5
4
3
2
1
V
SS
DQ14
DQ12
DQ10
DQ8
UDQM
A12
A8
V
SS
B
C
D
E
F
G
H
J
D/2
D
G
H
J
E
E/2
Pin Name
CLK
CS
0
~
1
CKE
A
0
~ A
12
BA
0
~ BA
1
RAS
A
A1
Pin Function
System Clock
Chip Select
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
*2: Top View
CAS
WE
L(U)DQM
DQ
0
~
15
V
DD
/V
SS
V
DDQ
/V
SSQ
Max. 0.20
Encapsulant
b
z
*1: Bottom View
< Top View
*2
>
#A1 Ball Origin Indicator
K4S511533C-XXXX
SAMSUNG
Week
[Unit:mm]
Symbol
A
A
1
E
E
1
D
D
1
e
b
z
Min
1.00
0.27
-
-
-
-
-
0.40
-
Typ
1.10
0.32
9.50
6.40
15.50
6.40
0.80
0.45
-
Max
1.30
0.37
-
-
-
-
-
0.50
0.10
Rev. 1.2 Dec. 2002
K4S511533C-YL/N/P
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
CMOS SDRAM
Unit
V
V
°C
W
mA
Notes :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
=Commercial, Extended and Industrial)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Symbol
V
DD
V
DDQ
V
IH
V
IL
V
OH
V
OL
I
LI
Min
2.7
2.7
2.2
-0.3
2.4
-
-10
Typ
3.0
3.0
3.0
0
-
-
-
Max
3.6
3.6
V
DDQ
+0.3
0.5
-
0.4
10
Unit
V
V
V
V
V
V
uA
1
2
I
OH
= -2mA
I
OL
= 2mA
3
Note
Notes :
1. V
IH
(max) = 5.3V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with tri-state outputs.
4. Dout is disabled, 0V
≤
V
OUT
≤
V
DDQ.
CAPACITANCE
Clock
(V
DD
= 3.0V or 3.3V, T
A
= 23°C, f = 1MHz, V
REF
=0.9V
±
50 mV)
Pin
Symbol
C
CLK
C
IN
C
IN
C
ADD
C
OUT
Min
3.0
3.0
1.5
3.0
6.0
Max
9.0
9.0
4.5
9.0
13.0
Unit
pF
pF
pF
pF
pF
Note
RAS, CAS, WE, CKE, DQM
CS
Address
DQ
0
~ DQ
15
Rev. 1.2 Dec. 2002
K4S511533C-YL/N/P
DC CHARACTERISTICS
CMOS SDRAM
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= Commercial, Extended and Industrial)
Parameter
Symbol
Burst length = 1
t
RC
≥
t
RC
(min)
I
O
= 0 mA
CKE
≤
V
IL
(max), t
CC
= 10ns
Test Condition
-80
Operating Current
(One Bank Active)
Precharge Standby Current
in power-down mode
I
CC1
*
I
CC2
P
100
Version
-1H
90
2
2
35
mA
25
8
8
45
35
mA
5
mA
-1L
85
mA
1.2
Unit
Note
I
CC2
PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC2
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
mA
Precharge Standby Current
in non power-down mode
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
I
CC2
NS
Input signals are stable
I
CC3
P*
CKE
≤
V
IL
(max), t
CC
= 10ns
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3
PS* CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC3
N*
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
mA
4
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
I
CC3
NS*
Input signals are stable
I
O
= 0 mA
Page burst
4Banks Activated
t
CCD
= 2CLKs
t
RC
≥
t
RC
(min)
-YL
CKE
≤
0.2V
Operating Current
(Burst Mode)
Refresh Current
I
CC4
*
145
125
115
mA
1.3
I
CC5
*
190
170
160
mA
6
7
Self Refresh Current
I
CC6
-YN
-YP
1800
uA
8
9
Notes :
1. Measured with outputs open
2. Measured with operating(Icc1) condition for 1chip and precharge stanby condition in non power down mode for 1chip(Icc2N).
(Icc1* = Icc1 +Icc2N)
3. Measured with operating(Icc4) condition for 1chip and active stanby condition in non power down mode for 1chip(Icc3N).
(Icc4* = Icc4 +Icc3N)
4. Measured with active stanby condition in power down mode for 1chip (Icc3P/PS) and precharge stanby condition in
power down mode for 1chip (Icc2P/PS). (Icc3P/PS* = Icc3P/PS +Icc2P/PS)
5. Measured with active stanby condition in non power down mode for 1chip (Icc3N/NS) and precharge stanby condition in
non power down mode for 1chip (Icc2N/NS). (Icc3N/NS* = Icc3N/NS +Icc2N/NS)
6. Refresh period is 64ms.
Measured with refresh condition for 1chip (Icc5) and precharge stanby condition in non power down mode for 1chip (Icc2N).
(Icc5* = Icc5 +Icc2N)
7. K4S511533C-YL**
8. K4S511533C-YN**
9. K4S511533C-YP**
10. Unless otherwise noted, input swing IeveI is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ)
Rev. 1.2 Dec. 2002
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