DATA SHEET
µ
PD488448 for Rev. E
128 M-bit Direct Rambus™ DRAM
MOS INTEGRATED CIRCUIT
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Description
Features
•
Low latency features
The Direct Rambus DRAM (Direct RDRAM) is a general purpose high-performance memory device suitable for use
in a broad range of applications including computer memory, graphics, video, and any other application where high
bandwidth and low latency are required.
The
µ
PD488448 is 128M-bit Direct Rambus DRAM (RDRAM), organized as 8M words by 16 bits.
The use of Rambus Signaling Level (RSL) technology permits 600 MHz to 800 MHz transfer rates while using
conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers
at 1.25 ns per two bytes (10 ns per sixteen bytes).
The architecture of the Direct RDRAMs allows the highest sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and data buses with independent row and column control yield
over 95% bus efficiency. The Direct RDRAM’s thirty-two banks support up to four simultaneous transactions.
System oriented features for mobile, graphics and large memory systems include power management, byte masking.
The
µ
PD488448 is offered in a CSP horizontal package suitable for desktop as well as low-profile add-in card and
mobile applications. Direct RDRAMs operate from a 2.5 volt supply.
•
Highest sustained bandwidth per DRAM device
- 1.6 GB/s sustained data transfer rate
- Separate control and data buses for maximized efficiency
- Separate row and column control buses for easy scheduling and highest performance
- 32 banks: four transactions can take place simultaneously at full bandwidth data rates
- Write buffer to reduce read latency
- Interleaved transactions
- 3 precharge mechanisms for controller flexibility
•
Advanced power management:
- Power-down self-refresh
- Multiple low power states allows flexibility in power consumption versus time to transition to active state
•
Organization: 1 Kbyte pages and 32 banks, x 16
•
Uses Rambus Signaling Level (RSL) for up to 800 MHz operation
•
Package: 62-pin TAPE FBGA and 62-pin PLASTIC FBGA (D
2
BGA (Die Dimension Ball Grid Array) )
Document No. E0041N11 (Ver. 1.1)
(Previous No. M14587EJ4V0DS00)
Date Published February 2006 CP (K)
Printed in Japan
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The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
This product became EOL in March, 2004.
Elpida
Memory, Inc. 2001-2006
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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PD488448 for Rev. E
Pin Description
Signal
SIO0, SIO1
Input / Output
Type
Note1
#pins
2
Description
Serial input/output. Pins for reading from and writing to the control registers using
a serial access protocol. Also used for power management.
Input / Output CMOS
CMD
Input
CMOS
Note1
Note1
1
Command input. Pins used in conjunction with SIO0 and SIO1 for reading from
and writing to the control registers. Also used for power management.
SCK
Input
CMOS
1
Serial clock input. Clock source used for reading from and writing to the control
registers.
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V
DD
V
DDa
V
CMOS
GND
GND
a
DQA7..DQA0
CFM
CFMN
V
REF
CTMN
CTM
RQ7..RQ5 or
ROW2..ROW0
RQ4..RQ0 or
COL4..COL0
DQB7..DQB0
NC
10
1
2
13
1
RSL
Note2
Supply voltage for the RDRAM core and interface logic.
Supply voltage for the RDRAM analog circuitry.
Supply voltage for CMOS input/output pins.
Ground reference for RDRAM core and interface.
Ground reference for RDRAM analog circuitry.
Data byte A. Eight pins which carry a byte of read or write data between the
Channel and the RDRAM.
Input / Output
8
Input
RSL
Note2
1
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
Total pin count per package
Notes 1.
All CMOS signals are high-true ; a high voltage is a logic one and a low voltage is logic zero.
2.
All RSL signals are low-true ; a low voltage is a logic one and a high voltage is logic zero.
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Input
RSL
Input
Input
RSL
Input
RSL
Input
Input / Output
RSL
Note2
1
Clock from master. Interface clock used for receiving RSL signals from the
Channel. Negative polarity.
1
RSL
Note2
Note2
Logic threshold reference voltage for RSL signals.
Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Negative polarity.
1
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Positive polarity.
Note2
Clock to master. Interface clock used for transmitting RSL signals to the Channel.
3
Row access control. Three pins containing control and address information for
row accesses.
RSL
Note2
Note2
5
Column access control. Five pins containing control and address information for
column accesses.
8
Data byte B. Eight pins which carry a byte of read or write data between the
Channel and the RDRAM.
2
These pins aren’t connected to inside of the chip.
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Data Sheet E0041N11
京公网安备 11010802033920号
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