K8F56(57)15ET(B)M
NOR FLASH MEMORY
256Mb M-die MLC NOR Specification
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1
Revision 1.2
September, 2006
K8F56(57)15ET(B)M
NOR FLASH MEMORY
Document Title
256M Bit (16M x16) Muxed Burst , Multi Bank MLC NOR Flash Memory
Revision History
Revision No. History
0.0
0.1
Initial
Revision
tCEZ is changed.
20ns==>15ns
44FBGA PKG diagram is added
Package diagram is added (New format)
DPD pin assignment is changed
D6 ==> C7
AC parameters are changed
tBA : 8ns ==> 9ns (@83MHz)
tBDH : 1.5ns
==> 3ns (@66Mhz, 83MHz), 2ns (@133Mhz)
tOE : 20ns ==> 15ns
tRDYA : 8ns ==> 9ns (@83MHz)
tRDYS : 4ns (@66Mhz, 83MHz), 1.5ns (@133Mhz)
==> 3ns (@66Mhz, 83MHz), 2ns (@133Mhz)
tOER : 20ns
==> 11ns (@66Mhz), 9ns (@83MHz), 6ns (@133Mhz)
Active write current
15mA (Typ.), 30mA (Max.)
==> 25mA (Typ.), 40mA (Max.)
Correct typo
Add Speed characteristic for 108Mhz Sync Burst Read
Add Ordering Information for Density
==> 56 : 256Mb for 66/83MHz
==> 57 : 267Mb for 108/133Mhz
Add Product Classification Table (Table 1-1)
Change tAVDH(AVD Hold Time from CLK)
6ns(@66MHz) ==> 2ns(@66MHz)
5ns(@83MHz) ==> 2ns(@83MHz)
Change tAAVDH(Address Hold Time from Rising Edge of AVD)
7ns(@66MHz) ==> 2ns(@66MHz)
5ns(@83MHz) ==> 2ns(@83MHz)
Change tCES(CE Setup Time to CLK)
4.5ns(@83/133MHz) ==> 6ns(@83/133MHz)
Change tOEZ(Output Disable to High Z
10ns(@66/83MHz) ==> 15ns(@66/83MHz)
Add Description and Figure of DPD
Correct typo
Move address tables to the end of specification
Correct note number on Command Sequence table
Change t
GHWL
(Read Recovery Time Before Write)
0ns(typ.) ==> 0ns(min.)
Change t
WP
(WE Pulse Width)
60ns(typ.) ==> 60ns(min.)
Change t
WPH
(WE Pulse Width High)
40ns(typ.) ==> 40ns(min.)
Draft Date
October 17, 2005
October 19, 2005
Remark
Preliminary
Preliminary
0.2
0.3
October 26,2005
Preliminary
November 10,2005 Preliminary
0.4
December 20,2005 Preliminary
0.5
January 05,2006
Preliminary
2
Revision 1.2
September, 2006
K8F56(57)15ET(B)M
Revision No. History
0.6
NOR FLASH MEMORY
Draft Date
April 04, 2006
Remark
Preliminary
CFI note is added (Max Operation frequency : Data 53H is in 66/
83Mhz part
1.0
tOEZ value is changed min 15ns to max 15ns
Specification is finalized
April 20,2006
1.1
Active Asynchronous read Current(@1Mhz) is changed
September 08, 2006
3mA(typ.),5mA(max.) to 8mA(typ.), 10mA(max.)
’In erase/program suspend followed by resume operation, min. 200ns
is needed for checking the busy status’ is added
Frequency information is added to Programmable Wait State at Burst
Mode Configuration Register Table.
" Asynchronous mode may not support read following four sequential
invalid read condition within 200ns." is added
Correct typo
September 28, 2006
1.2
3
Revision 1.2
September, 2006
K8F56(57)15ET(B)M
NOR FLASH MEMORY
256M Bit (16M x16) Muxed Burst , Multi Bank MLC NOR Flash Memory
FEATURES
GENERAL DESCRIPTION
•
Single Voltage, 1.7V to 1.95V for Read and Write operations
The K8F56(57)15E featuring single 1.8V power supply is a
•
Organization
256Mbit Muxed Burst Multi Bank Flash Memory organized as
- 16,777,216 x 16 bit (Word Mode Only)
16Mx16. The memory architecture of the device is designed to
•
Multiplexed Data and Address for reduction of interconnections
divide its memory arrays into 259 blocks with independent hard-
- A/DQ0 ~ A/DQ15
ware protection. This block architecture provides highly flexible
•
Read While Program/Erase Operation
erase and program capability. The K8F56(57)15E NOR Flash
•
Multiple Bank Architecture
consists of sixteen banks. This device is capable of reading
- 16 Banks (16Mb Partition)
data from one bank while programming or erasing in the other
•
OTP Block : Extra 512-Word block
bank.
•
Read Access Time (@ C
L
=30pF)
Regarding read access time, the K8F5615E provides an 11ns
- Asynchronous Random Access Time : 100ns
burst access time and an 100ns initial access time at 66MHz. At
- Synchronous Random Access Time : 100ns
- Burst Access Time :
83MHz, the K8F5615E provides an 9ns burst access time and
11ns (66MHz), 9ns(83MHz), 7ns (108MHz), 6ns(133MHz)
an 100ns initial access time. At 108MHz, the K8F5715E pro-
•
Burst Length :
vides an 7ns burst access time and an 100ns initial access
- Continuous Linear Burst
time. At 133MHz, the K8F5715E provides an 6ns burst access
- Linear Burst : 8-word & 16-word with No-wrap & Wrap
time and an 100ns initial access time.The device performs a
•
Block Architecture
program operation in units of 16 bits (Word) and erases in units
- Four 16Kword blocks and two hundreds fifty-five 64Kword blocks
of a block. Single or multiple blocks can be erased. The block
- Bank 0 contains four 16 Kword blocks and fifteen 64Kword blocks
erase operation is completed within typically 0.6sec. The device
- Bank 1 ~ Bank 15 contain two hundred forty 64Kword blocks
requires 25mA as program/erase current in the extended tem-
•
Reduce program time using the V
PP
perature ranges.
•
Support 32 words Buffer Program
The K8F56(57)15E NOR Flash Memory is created by using
•
Power Consumption (Typical value, C
L
=30pF)
Samsung's advanced CMOS process technology. This device is
- Synchronous Read Current : 35mA at 133MHz
available in 44ball / 88 ball FBGA package.
- Program/Erase Current : 25mA
- Read While Program/Erase Current : 45mA
PIN DESCRIPTION
- Standby Mode/Auto Sleep Mode : 30uA
Pin Name
Pin Function
•
Block Protection/Unprotection
- Using the software command sequence
A16 - A23
Address Inputs
- Last two boot blocks are protected by WP=V
IL
- All blocks are protected by V
PP
=V
IL
A/DQ0 - A/DQ15 Multiplexed Address/Data input/output
•
Handshaking Feature
CE
Chip Enable
- Provides host system with minimum latency by monitoring RDY
•
Erase Suspend/Resume
OE
Output Enable
•
Program Suspend/Resume
•
Unlock Bypass Program/Erase
RESET
Hardware Reset
•
Hardware Reset (RESET)
•
Data Polling and Toggle Bits
V
PP
Accelerates Programming
- Provides a software method of detecting the status of program
WE
Write Enable
or erase completion
•
Endurance
WP
Hardware Write Protection Input
100K Program/Erase Cycles Minimum
•
Data Retention : 10 years
CLK
Clock
•
Extended Temperature : -25°C ~ 85°C
•
Support Common Flash Memory Interface
RDY
Ready Output
•
Low Vcc Write Inhibit
AVD
Address Valid Input
•
Package : 88 - ball FBGA Type (8mm x 11mm),
0.8 mm ball pitch,
DPD
Deep Power Down
1.2mm (Max.) Thickness
44 - ball FBGA Type (8mm x 9mm),
0.5 mm ball pitch,
1.0mm (Max.) Thickness
Vcc
V
SS
Power Supply
Ground
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
4
Revision 1.2
September, 2006
K8F56(57)15ET(B)M
88 Ball FBGA TOP VIEW (BALL DOWN)
NOR FLASH MEMORY
1
2
3
4
5
6
7
8
A
DU
DU
DU
DU
B
NC
NC
WP
Vss
VCC
VCC
NC
NC
C
A20
RFU
NC
Vss
RFU
CLK
DPD
NC
D
NC
A23
RFU
NC
RFU
NC
NC
NC
E
A21
NC
NC
NC
AVD
VPP
A17
A22
F
A16
NC
RFU
RESET
WE
A19
NC
A18
G
NC
A/DQ7
A/DQ13
A/DQ5
A/DQ10
A/DQ2
RDY
NC
H
RFU
A/DQ15
A/DQ14
A/DQ12
A/DQ3
A/DQ1
A/DQ8
NC
J
RFU
OE
A/DQ6
A/DQ4
A/DQ11
A/DQ9
A/DQ0
Vccq
K
CE
RFU
RFU
RFU
Vccq
VCC
Vccq
RFU
L
V
SS
Vss
Vccq
VCC
Vss
Vss
Vss
Vss
M
DU
DU
DU
DU
5
Revision 1.2
September, 2006