K8A6415ET(B)C
NOR Flash Memory
64Mb C-die SLC NOR Specification
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1
Revision 1.0
November 2008
K8A6415ET(B)C
NOR Flash Memory
Document Title
64M Bit (4M x16) Sync Burst / Page Mode / Multi-Bank NOR Flash Memory
Revision History
Revision No.
0.0
0.1
Initial draft
- 88FBGA Package is added
- Endurance : 100,000 Program/Erase Cycles is added
0.2
- 88FBGA Package thickness is changed max 1.2mm to 1.1mm.
- tCES is changed 4ns to 6ns(@54Mhz)/4ns to 6ns(@66Mhz)/4ns to
4.5ns(@83Mhz)/3.5ns to 4ns(@108Mhz)
- tCLK parameter is added.
- tCLKL/H is changed to 0.4xtCLK(min)/0.6xtCLK(max)
- tCLKHCL is changed max 3ns to 2.5ns(@83Mhz)/2ns to
1.5ns(@108Mhz)
- ’including CLK characterization’ is added in Input Pulse and Test Point
(AC test condition)
0.3
- Package code ’H’ is added in ordering information
H : FBGA(Lead Free, OSP, Halogen Free)
- Extended Configuration Register option is added
- Enhanced Block Protection option is added
- tCES @ 108MHz in AC Parameter table is changed from Min. 4.0ns to
Min. 4.5ns.
Jan. 03, 2008
Jul. 04, 2008
Nov. 13, 2008
Target
Preliminary
History
Draft Date
Nov. 05, 2007
Jul. 28, 2006
Nov. 23, 2007
Dec. 20, 2007
Remark
Target
Target
Target
Target
0.5
1.0
2
Revision 1.0
November 2008
K8A6415ET(B)C
64Mb C-die SLC NOR Specification 1
NOR Flash Memory
1.0 FEATURES................................................................................................................................................................. 3
1.1. GENERAL DESCRIPTION ..................................................................................................................................... 3
1.2. PIN DESCRIPTION ................................................................................................................................................ 4
1.3. FUNCTIONAL BLOCK DIAGRAM.......................................................................................................................... 5
1.4. 88 Ball FBGA Top view (Ball down)........................................................................................................................ 6
2.0 ORDERING INFORMATION ...................................................................................................................................... 7
3.0 PRODUCT INTRODUCTION ..................................................................................................................................... 9
4.0 COMMAND DEFINITIONS ......................................................................................................................................... 10
5.0 DEVICE OPERATION ................................................................................................................................................ 12
5.1. Read Mode ............................................................................................................................................................. 12
5.2. Asynchronous Read Mode ..................................................................................................................................... 12
5.3. Synchronous (Burst) Read Mode ........................................................................................................................... 12
5.4. Output Driver Setting .............................................................................................................................................. 13
5.5. Programmable Wait State....................................................................................................................................... 13
5.6. Set Burst Mode Configuration Register .................................................................................................................. 13
5.6.1
Extended Configuration Register (option : K8A6215ET(B)C, K8A6515ET(B)C only) ........................................ 14
5.7. Programmable Wait State Configuration ................................................................................................................ 14
5.8. Burst Read Mode Setting........................................................................................................................................ 14
5.9. RDY Configuration.................................................................................................................................................. 14
5.10. Autoselect Mode ................................................................................................................................................... 14
5.11. Standby Mode....................................................................................................................................................... 15
5.12. Automatic Sleep Mode.......................................................................................................................................... 15
5.13. Output Disable Mode ............................................................................................................................................ 15
5.14. Block Protection & Unprotection ........................................................................................................................... 15
5.14.1 Enhanced Block Protection (option : K8A6315ET(B)C, K8A6515ET(B)C only) ................................................. 15
5.15. Hardware Reset.................................................................................................................................................... 20
5.16. Software Reset ..................................................................................................................................................... 20
5.17. Program ................................................................................................................................................................ 20
5.18. Accelerated Program Operation ........................................................................................................................... 20
5.19. Unlock Bypass ...................................................................................................................................................... 21
5.20. Chip Erase ............................................................................................................................................................ 21
5.21. Block Erase........................................................................................................................................................... 21
5.22. Erase Suspend / Resume..................................................................................................................................... 21
5.23. Program Suspend / Resume ................................................................................................................................ 22
5.24. Read While Write Operation ................................................................................................................................. 22
5.25. OTP Block Region ................................................................................................................................................ 22
5.26. Low VCC Write Inhibit........................................................................................................................................... 22
5.27. Write Pulse “Glitch” Protection.............................................................................................................................. 22
5.28. Logical Inhibit........................................................................................................................................................ 22
5.29. Power-up Protection ............................................................................................................................................. 23
5.30. FLASH MEMORY STATUS FLAGS ..................................................................................................................... 23
6.0 Commom Flash Memory Interface ............................................................................................................................. 25
7.0 ABSOLUTE MAXIMUM RATINGS
....................................................................................................................... 27
8.0 RECOMMENDED OPERATING CONDITIONS ( Voltage reference to GND )
....................................................... 27
9.0 DC CHARACTERISTICS
..................................................................................................................................... 27
10.0 CAPACITANCE(TA = 25 ×C, VCC = 1.8V, f = 1.0MHz)
...................................................................................... 29
11.0 AC TEST CONDITION.......................................................................................................................................
29
12.0 AC CHARACTERISTICS.......................................................................................................................................... 30
12.1. Synchronous/Burst Read
............................................................................................................................... 30
12.2. Asynchronous Read.......................................................................................................................................
33
12.3. Hardware Reset(RESET)
............................................................................................................................... 35
12.4. Erase/Program Operation
.............................................................................................................................. 36
1
Revision 1.0
November 2008
K8A6415ET(B)C
NOR Flash Memory
13.0 FLASH Erase/Program Performance..................................................................................................................
36
14.0 Crossing of First Word Boundary in Burst Read Mode............................................................................................. 42
15.0 PACKAGE DIMENSIONS......................................................................................................................................... 52
2
Revision 1.0
November 2008
K8A6415ET(B)C
NOR Flash Memory
64M Bit (4M x16) Sync Burst / Page Mode / Multi-Bank NOR Flash Memory
1.0 FEATURES
•
Single Voltage, 1.7V to 1.95V for Read and Write operations
•
Organization
- 4,194,304 x 16 bit (Word Mode Only)
•
Read While Program/Erase Operation
•
Multiple Bank Architecture
- 16 Banks (4Mb Partition)
•
OTP Block : Extra 256word block
•
Read Access Time (@ C
L
=30pF)
- Asynchronous Random Access Time : 70ns
- Synchronous Random Access Time : 70ns
- Burst Access Time :
14.5ns (54MHz) / 11ns (66MHz) / 9ns (83Mhz) / 7ns (108Mhz)
•
Page Mode Operation
8-Words Page access allows fast asychronous read
Page Read Access Time : 20ns
•
Burst Length :
- Continuous Linear Burst
- Linear Burst : 8-word & 16-word with Wrap
•
Block Architecture
- Eight 4Kword blocks and one hundred twenty seven 32Kword
blocks
- Bank 0 contains eight 4 Kword blocks and seven 32Kword
blocks
- Bank 1~Bank 15 contain one hundred twenty 32Kword blocks
•
Reduce program time using the V
PP
•
Support Single & Quad word accelerate program
•
Power Consumption (Typical value, C
L
=30pF)
- Async/Sync burst Access Current : 24mA
- Program/Erase Current : 15mA
- Read While Program/Erase Current : 40mA
- Standby Mode/Auto Sleep Mode :15uA
•
Block Protection/Unprotection
- Using the software command sequence
- Last two boot blocks are protected by WP=V
IL
- All blocks are protected by V
PP
=V
IL
•
Handshaking Feature
- Provides host system with minimum latency by monitoring
RDY
•
Erase Suspend/Resume
•
Program Suspend/Resume
•
Unlock Bypass Program/Erase
•
Hardware Reset (RESET)
•
Data Polling and Toggle Bits
- Provides a software method of detecting the status of program
or erase completion
•
Endurance : 100,000 Program/Erase Cycles
•
Extended Temperature : -25°C ~ 85°C
•
Support Common Flash Memory Interface
•
Low Vcc Write Inhibit
•
Package : 88 - ball FBGA Type (8mm x 11mm),
0.8 mm ball pitch,
1.1mm (Max.) Thickness
1.1 GENERAL DESCRIPTION
The K8A6415E featuring single 1.8V power supply is a 64Mbit Syn-
chronous Burst Multi Bank Flash Memory organized as 4Mx16. The
memory architecture of the device is designed to divide its memory
arrays into 135 blocks with independent hardware protection. This
block architecture provides highly flexible erase and program capabil-
ity. The K8A6415E NOR Flash consists of sixteen banks. This device
is capable of reading data from one bank while programming or eras-
ing in the other bank.
Regarding read access time, the K8A6415E provides an 14.5ns burst
access time and an 70ns initial access time at 54MHz. At 66MHz, the
K8A6415E provides an 11ns burst access time and 70ns initial access
time. At 83MHz, the K8A6415E provides an 9ns burst access time
and 70ns initial access time. At 108MHz, the K8A6415E provides an
7ns burst access time and 70ns initial access time. The device per-
forms a program operation in units of 16 bits (Word) and an erase
operation in units of a block. Single or multiple blocks can be erased.
The block erase operation is completed within typically 0.7sec. The
device requires 15mA as program/erase current in the extended tem-
perature ranges.
The K8A6415E NOR Flash Memory is created by using Samsung's
advanced CMOS process technology.
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
3
Revision 1.0
November 2008
京公网安备 11010802033920号
EEWORLD
