K4D551638H
256M GDDR SDRAM
256Mbit GDDR SDRAM
Revision 1.3
April 2007
Notice
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev. 1.3 April 2007
K4D551638H
Revision History
Revision
0.0
0.1
0.2
Month
July
September
November
Year
2005
2005
2005
- Target Spec
- Defined Target Specification
- Preliminary Spec
- Changed CL from 4clk to 3clk of -LC40
- Added current spec
- Added IBIS data
- Final Spec
- Deleted -LC33/36/60 spec.
History
256M GDDR SDRAM
1.0
1.1
1.2
1.3
January
April
April
April
2006
2006
2006
2007
- Deleted CL4 option in MRS table according to deleting high frequency bin(-LC33/36).
- Added CL2.5 option(-LC50 can support 166MHz@CL 2.5)
- Changed VDD(min) spec from 2.5V to 2.35V.
- Corrected typo on page 14.
- 2 -
Rev. 1.3 April 2007
K4D551638H
256M GDDR SDRAM
4M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
1.0 FEATURES
• 2.35V ~ 2.7V power supply for device operation
• 2.35V ~ 2.7V power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 2.5, 3 (clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going
edge of the system clock
• Differential clock input
• No Write-Interrupted by Read Function
(WIR function can be supported only for 200/166MHz)
• 2 DQS’s (1DQS / Byte)
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 64ms refresh period (8K cycle)
• 66pin TSOP-II lead free package(RoHS Compliant)
• Maximum clock frequency up to250MHz
• Maximum data rate up to 500Mbps/pin
2.0 ORDERING INFORMATION
Part NO.
K4D551638H-LC40
K4D551638H-LC50
Max Freq.
250MHz
200MHz
Max Data Rate
500Mbps/pin
400Mbps/pin
Interface
SSTL_2
VDD & VDDQ
2.35V ~
2.7V
Package
66pin TSOP-II
3.0 GENERAL DESCRIPTION
FOR 4M x 16Bit x 4 Bank GDDR SDRAM
The K4D551638H is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 4,194,304 words by 16 bits, fab-
ricated with SAMSUNG
’
s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high perfor-
mance up to 1.1GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies,
programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system
applications.
- 3 -
Rev. 1.3 April 2007
K4D551638H
4.0 PIN CONFIGURATION
(Top View)
256M GDDR SDRAM
V
DD
DQ
0
V
DDQ
DQ
1
DQ
2
V
SSQ
DQ
3
DQ
4
V
DDQ
DQ
5
DQ
6
V
SSQ
DQ
7
NC
V
DDQ
LDQS
NC
V
DD
NC
LDM
WE
CAS
RAS
CS
NC
BA
0
BA
1
AP/A
10
A
0
A
1
A
2
A
3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
V
SS
DQ
15
V
SSQ
DQ
14
DQ
13
V
DDQ
DQ
12
DQ
11
V
SSQ
DQ
10
DQ
9
V
DDQ
DQ
8
NC
V
SSQ
UDQS
NC
V
REF
V
SS
UDM
CK
CK
CKE
NC
A
12
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm Pin Pitch)
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
PIN DESCRIPTION
CK,CK
CKE
CS
RAS
CAS
WE
L(U)DQS
L(U)DM
RFU
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe
Data Mask
Reserved for Future Use
BA
0
, BA
1
A
0
~A
12
DQ
0
~ DQ
15
V
DD
V
SS
V
DDQ
V
SSQ
NC
VREF
Bank Select Address
Address Input
Data Input/Output
Power
Ground
Power for DQ
’
s
Ground for DQ
’
s
No Connection
Reference voltage
- 4 -
Rev. 1.3 April 2007
K4D551638H
5.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
CK,
CK
*1
Type
Input
Function
256M GDDR SDRAM
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s that are
sampled on both edges of the DQS.
Activates the CK signal when high and deactivates the CK signal when low. By deactivating
the clock, CKE low indicates the Power down mode or Self refresh mode.CKE is synchronous
for Power down entry and exit, and for Self refresh entry. CKE is asynchronous for Self
refresh exit, and for output disable. CKE must be maintained high through Read and Write
accesses. Input buffers, excluding CK, CK and CKE are disbled during Power down. Input
buffers, excluding CKE are disabled during Self refresh. CKE is an SSTL_2 input, but will
detect a LVCMOS low level after Vdd is applied upon 1st power up. After Vref has become
stable during the power on and intialization sequence, it must be maintained for proper oper-
ation of the CKE receiver. For proper Self refresh entry and exit, Vref must be maintained to
this input.
CS enables the command decoder when low and disabled the command decoder when high.
When the command decoder is disabled, new commands are ignored but previous operations
continue.
Latches row addresses on the positive going edge of the CK with RAS low. Enables row
access & precharge.
Latches column addresses on the positive going edge of the CK with CAS low. Enables col-
umn access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Data input and output are synchronized with both edge of DQS.
For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on
DQ8-DQ15.
Data in Mask. Data In is masked by DM Latency=0 when DM is
high in burst write. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons
to the data on DQ8-DQ15.
Data inputs/Outputs are multiplexed on the same pins.
Selects which bank is to be active.
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA12, Column addresses : CA0 ~ CA8.
Power and ground for the input buffers and core logic.
Isolated power supply and ground for the output buffers to provide improved noise immunity.
Reference voltage for inputs, used for SSTL interface.
CKE
Input
CS
Input
RAS
CAS
WE
Input
Input
Input
LDQS,UDQS
Input/Output
LDM,UDM
DQ0 ~ DQ15
BA0, BA1
A0 ~ A12
V
DD
/V
SS
V
DDQ
/V
SSQ
V
REF
NC/RFU
Input
Input/Output
Input
Input
Power Supply
Power Supply
Power Supply
No connection/
This pin is recommended to be left "No connection" on the device
Reserved for future use
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply V
REF
to CK pin.
- 5 -
Rev. 1.3 April 2007
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