IC PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, PLASTIC, SOT-362, TSSOP-48, Clock Driver
PCKV856DGG Parametric
Parameter Name
Attribute value
Maker
NXP
Parts packaging code
TSSOP
package instruction
TSSOP,
Contacts
48
Reach Compliance Code
unknown
Input adjustment
DIFFERENTIAL
JESD-30 code
R-PDSO-G48
JESD-609 code
e4
length
12.5 mm
Logic integrated circuit type
PLL BASED CLOCK DRIVER
Number of functions
1
Number of inverted outputs
Number of terminals
48
Actual output times
10
Maximum operating temperature
70 °C
Minimum operating temperature
Package body material
PLASTIC/EPOXY
encapsulated code
TSSOP
Package shape
RECTANGULAR
Package form
SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Certification status
Not Qualified
Same Edge Skew-Max（tskwd）
0.2 ns
Maximum seat height
1.2 mm
Maximum supply voltage (Vsup)
2.7 V
Minimum supply voltage (Vsup)
2.3 V
Nominal supply voltage (Vsup)
2.5 V
surface mount
YES
Temperature level
COMMERCIAL
Terminal surface
NICKEL PALLADIUM GOLD
Terminal form
GULL WING
Terminal pitch
0.5 mm
Terminal location
DUAL
width
6.1 mm
PCKV856DGG Preview
INTEGRATED CIRCUITS
PCKV856
70–170 MHz I
2
C differential 1:10
clock driver
Preliminary specification
2000 Sep 06
Philips
Semiconductors
Philips Semiconductors
Preliminary specification
70–170 MHz I
2
C differential 1:10 clock driver
PCKV856
FEATURES
•
Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications
PIN CONFIGURATION
GND 1
Y
0
2
Y
0
3
V
DDQ
4
Y
1
5
Y
1
6
GND 7
GND 8
Y
2
9
Y
2
10
V
DDQ
11
SCL 12
CLK 13
CLK 14
V
DD
I
2
C 15
AV
CC
16
AGND 17
GND 18
Y
3
19
Y
3
20
V
DDQ
21
Y
4
22
48 GND
47 Y
5
46 Y
5
45 V
DDQ
44 Y
6
43 Y
6
42 GND
41 GND
40 Y
7
39 Y
7
38 V
DDQ
37 SDA
36 FB
IN
35 FB
IN
34 V
DDQ
33 FB
OUT
32 FB
OUT
31 GND
30 Y
8
29 Y
8
28 V
DDQ
27 Y
9
26 Y
9
25 GND
•
Individual output enable/disable capability via I
2
C
•
Reference inputs selectable between HCSL and SSTL via I
2
C
•
1-to-10 differential clock distribution
•
Very low skew (< 100 ps) and jitter (< 100 ps)
•
2.5 V AV
CC
and 2.5 V V
DDQ
•
SSTL_2 interface clock inputs and outputs
•
CMOS control signal input
•
Test mode enables buffers while disabling PLL
•
Low current power-down mode
•
Tolerant of Spread Spectrum input clock
•
Full DDR solution provided when used with SSTL16877 or
SSTV16857
•
See PCKV857 for non I
2
C applications
DESCRIPTION
Zero delay buffer to distribute an SSTL differential clock input pair to
10 SSTL_2 differential output pairs. Outputs are slope controlled.
External feedback pin for synchronization of the outputs to the input.
A CMOS style Enable/Disable pin is provided for low power disable.
The PCKV856 features I
2
C compatibility by introduction of SCL
(Serial Clock Line) on pin 12 and SDA (Serial Data Line) on pin 37.
This provides flexibility in configuring the I/Os of the PCKV856.
Y
4
23
GND 24
SW00425
ORDERING INFORMATION
PACKAGES
48-Pin Plastic TSSOP
TEMPERATURE RANGE
0°C to +70°C
ORDER CODE
PCKV856 DGG
DRAWING NUMBER
SOT362-1
PINS
1, 7, 8, 18, 24, 25, 31, 41, 42, 48
2, 3, 5, 6, 9, 10, 19, 20, 22, 23, 26, 27, 29,
30, 32, 33, 39, 40, 43, 44, 46, 47
4, 11, 21, 28, 34
13, 14, 35, 36, 38, 45
16
17
37
12
15
SYMBOL
GND
Y
n
, Y
n
, FB
OUT
, FB
OUT
V
DDQ
CLK
IN
, CLK
IN
, FB
IN
, FB
IN
AV
CC
AGND
SDA
SCL
V
DD
I
2
C
DESCRIPTION
SSTL_2 ground pins
SSTL_2 differential outputs
SSTL_2 power pins
SSTL_2 differential inputs
Analog power
Analog ground
Serial data
Serial clock
I
2
C power
2000 Sep 06
2
Philips Semiconductors
Preliminary specification
70–170 MHz I
2
C differential 1:10 clock driver
PCKV856
FUNCTION TABLE
INPUTS
G
L
L
H
H
X
2
CLK
L
H
L
H
<
20 MHz
CLK
H
L
H
L
<
20 MHz
Y
Z
Z
L
H
Z
Y
Z
Z
H
L
Z
OUTPUTS
FB
OUT
Z
1
Z
1
L
H
Z
1
FB
OUT
Z
1
Z
1
H
L
Z
1
OFF
OFF
ON
ON
OFF
PLL ON/OFF
NOTES:
H = HIGH voltage level
L = LOW voltage level
Z = high impedance OFF-state
X = don’t care
1. Subject to change. May cause conflict with FB
IN
pins.
2. Additional feature that senses when the clock input is less than 20 MHz and places the part in sleep mode.
BLOCK DIAGRAM
SDA
SCL
I
2
C
CONTROL
LOGIC
Y
0
Y
0
Y
1
Y
1
Y
2
Y
2
Y
3
Y
3
Y
4
CLK
CLK
FB
IN
FB
IN
AV
CC
Y
4
PLL
Y
5
Y
5
Y
6
Y
6
Y
7
Y
7
Y
8
Y
8
Y
9
Y
9
FB
OUT
FB
OUT
SW00426
I
2
C ADDRESS
1
1
0
1
0
0
1
R/W
su01394
2000 Sep 06
3
Philips Semiconductors
Preliminary specification
70–170 MHz I
2
C differential 1:10 clock driver
PCKV856
I
2
C CONSIDERATIONS
I
2
C has been chosen as the serial bus interface to control the PCKV856. I
2
C was chosen to support the JEDEC proposal JC-42.5 168 Pin
Unbuffered SDRAM DIMM. All vendors are required to determine the legal issues associated with the manufacture of I
2
C devices.
1) Address assignment: The clock driver in this specification uses the single, 7-bit address shown below. All devices can use the address if only
one master clock driver is used in a design. The address can be re-used for the CKBF device if no other conflicting I
2
C clock driver is used in
the system.
The following address was confirmed by Philips on 09/04/96.
A6
A5
A4
A3
A2
A1
A0
R/W
1
1
0
1
0
0
1
0
2
C controller as a data direction bit. A ‘zero’ indicates a transmission (WRITE) to the clock device. A ‘one’
NOTE:
The R/W bit is used by the I
indicates a request for data (READ) from the clock driver. Since the definition of the clock buffer only allows the controller to WRITE data; the
R/W bit of the address will always be seen as ‘zero’. Optimal address decoding of this bit is left to the vendor.
2) Options: It is our understanding that metal mask options and other pinouts of this type of clock driver will be allowed to use the same address
as the original CKBF device. I
2
C addresses are defined in terms of function (master clock driver) rather than form (pinout, and option).
3) Slave/Receiver: The clock driver is assumed to require only slave/receiver functionality. Slave/transmitter functionality is optional.
4) Data Transfer Rate: 100 kbits/s (standard mode) is the base functionality required. Fast mode (400 kbits/s) functionality is optional.
5) Logic Levels: I
2
C logic levels are based on a percentage of V
DD
for the controller and other devices on the bus. Assume all devices are
based on a 3.3 Volt supply.
6) Data Byte Format: Byte format is 8 Bits as described in the following appendices.
7) Data Protocol: To simplify the clock I
2
C interface, the clock driver serial protocol was specified to use only block writes from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. Indexed bytes are not allowed. However, the SMBus controller has a more specific format than the generic I
2
C protocol.
The clock driver must meet this protocol which is more rigorous than previously stated I
2
C protocol. Treat the description from the viewpoint of
controller. The controller ‘‘writes” to the clock driver and if possible would ‘‘read” from the clock driver (the clock driver is a slave/receiver only
and is incapable of this transaction.)
‘‘The block write begins with a slave address and a write condition. After the command code the host (controller) issues a byte count which
describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be the number 20 (14h),
followed by the 20 bytes of data. The byte count may not be 0. A block write command is allowed to transfer a maximum of 32 data bytes.”
1 bit
Start bit
7 bits
Slave Address
1
R/W
1
Ack
8 bits
Command Code
1
Ack
Byte Count = N
Ack
1 bit
Data Byte 1
8 bits
Ack
1
Data Byte 2
8 bits
Ack
1
...
Data Byte 2
8 bits
Ack
1
Stop
1
SW00279
NOTE:
The acknowledgement bit is returned by the slave/receiver (the clock driver).
Consider the command code and the byte count bytes required as the first two bytes of any transfer. The command code is software
programmable via the controller, but will be specified as 0000 0000 in the clock specification. The byte count byte is the number of additional
bytes required to transfer, not counting the command code and byte count bytes. Additionally, the byte count byte is required to be a minimum of
1 byte and a maximum of 32 bytes to satisfy the above requirement.
2000 Sep 06
4
Philips Semiconductors
Preliminary specification
70–170 MHz I
2
C differential 1:10 clock driver
PCKV856
For example:
Byte count byte
MSB
0000
0000
0000
0000
0000
0000
0000
0000
0010
LSB
0000 Not allowed. Must have at least one byte.
0001 Data for functional and frequency select register (currently byte 0 in spec)
0010 Reads first two bytes of data. (byte 0 then byte 1)
0011
Reads first three bytes (byte 0, 1, 2 in order)
Notes:
0100 Reads first four bytes (byte 0, 1, 2, 3 in order)
0101 Reads first five bytes (byte 0, 1, 2, 3, 4 in order)
0110 Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)
0111
Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)
0000 Max byte count supported = 32
A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The serial controller interface
can be simplified by discarding the information in both the command code and the byte count bytes and simply reading all the bytes that are
sent to the clock driver after being addressed by the controller. It is expected that the controller will not provide more bytes than the clock driver
can handle. A clock vendor may choose to discard any number of bytes that exceed the defined byte count.
8) Clock stretching: The clock device must not hold/stretch the SCLOCK or SDATA lines low for more than 10 ms. Clock stretching is
discouraged and should only be used as a last resort. Stretching the clock/data lines for longer than this time puts the device in an error/time-out
mode and may not be supported in all platforms. It is assumed that all data transfers can be completed as specified without the use of
clock/data stretching.
9) General Call: It is assumed that the clock driver will not have to respond to the ‘‘general call.”
10) Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in section 15 of the I
2
C
specification.
a) Pull-Up Resistors: Any internal resistors pull-ups on the SDATA and SCLOCK inputs must be stated in the individual datasheet. The use of
internal pull-ups on these pins of below 100 kΩ is discouraged. Assume that the board designer will use a single external pull-up resistor for
each line and that these values are in the 5–6 kΩ range. Assume one I
2
C device per DIMM (serial presence detect), one I
2
C controller, one
clock driver plus one/two more I
2
C devices on the platform for capacitive loading purposes.
(b) Input Glitch Filters: Only fast mode I
2
C devices require input glitch filters to suppress bus noise. The clock driver is specified as a standard
mode device and is not required to support this feature.
11) PWR DWN: If a clock driver is placed in PWR DWN mode, the SDATA and SCLK inputs must be 3-Stated and the device must retain all
programming information. I
dd
current due to the I
2
C circuitry must be characterized and in the data sheet.
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