DS1013M-55 datasheet, PDF - EEWORLD Datasheet

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DS1013M-55: DescriptionSilicon Delay Line, 3-Func, 1-Tap, True Output, CMOS, PDIP8, 0.300 INCH, PLASTIC, MS-001AB, DIP-8; Categorylogic logic; File Size49KB，6 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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DS1013M-55 Overview

Silicon Delay Line, 3-Func, 1-Tap, True Output, CMOS, PDIP8, 0.300 INCH, PLASTIC, MS-001AB, DIP-8

DS1013M-55 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Maxim
Parts packaging code	DIP
package instruction	0.300 INCH, PLASTIC, MS-001AB, DIP-8
Contacts	8
Reach Compliance Code	not_compliant
Other features	BOTH LEADING & TRAILING EDGE ACCURACY; MAX FAN OUT OF 10 74LS LOAD PER OUTPUT
series	CMOS
JESD-30 code	R-PDIP-T8
JESD-609 code	e0
length	9.375 mm
Logic integrated circuit type	SILICON DELAY LINE
Number of functions	3
Number of taps/steps	1
Number of terminals	8
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP8,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	70 mA
programmable delay line	NO
Prop。Delay @ Nom-Sup	55 ns
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Total delay nominal (td)	55 ns
width	7.62 mm

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DS1013

3-in-1 Silicon Delay Line

www.dalsemi.com

FEATURES

All-silicon time delay

3 independent buffered delays

Delay tolerance ±2ns for -10 through –60

Stable and precise over temperature and

voltage range

Leading and trailing edge accuracy

Economical

Auto-insertable, low profile

Standard 14-pin DIP, 8-pin DIP, or 16-pin

SOIC

Low-power CMOS

TTL/CMOS-compatible

Vapor phase, IR and wave solderable

Custom delays available

Quick turn prototypes

Extended temperature ranges available

PIN ASSIGNMENT

IN 1

IN 2

IN 3

GND

OUT 1

OUT 2

IN 1

IN 2

IN 3

OUT 1

OUT 2

OUT 3

OUT 3 GND

DS1013 14-pin DIP (300-mil)

See Mech. Drawings Section

DS1013S 16-pin SOIC

(300-mil)

See Mech. Drawings Section

OUT 1

OUT 2

OUT 3

IN 1

IN 2

IN 3

GND

DS1013M 8-pin DIP (300-mil)

See Mech. Drawings Section

PIN DESCRIPTION

IN 1, IN 2, IN 3

OUT 1, OUT 2, OUT 3

GND

- Inputs

- Outputs

- Ground

- +5 Volts

- No Connection

DESCRIPTION

The DS1013 series of delay lines has three independent logic buffered delays in a single package. The

devices are offered in a standard 14-pin DIP which is pin-compatible with hybrid delay lines. Alternative

8-pin DIP and surface mount packages are available which save PC board area. Since the DS1013

products are an all silicon solution, better economy is achieved when compared to older methods using

hybrid techniques. The DS1013 series delay lines provide a nominal accuracy of

±2ns

for delay times

ranging from 10 ns to 60 ns, increasing to 5% for delays of 150 ns and longer. The DS1013 delay line

reproduces the input logic state at the output after a fixed delay as specified by the dash number extension

of the part number. The DS1013 is designed to reproduce both leading and trailing edges with equal

precision. Each output is capable of driving up to 10 74LS loads. Dallas Semiconductor can customize

standard products to meet special needs. For special requests and rapid delivery, call (972) 371–4348.

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