H5TQ2G83DFR-PBJ datasheet, PDF

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H5TQ2G83DFR-PBJ: DescriptionDDR DRAM, 256MX8, 0.225ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78; Categorystorage storage; File Size635KB，34 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/; Environmental Compliance

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H5TQ2G83DFR-PBJ Overview

DDR DRAM, 256MX8, 0.225ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78

H5TQ2G83DFR-PBJ Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SK Hynix
Parts packaging code	BGA
package instruction	TFBGA, BGA78,9X13,32
Contacts	78
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	MULTI BANK PAGE BURST
Maximum access time	0.225 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	800 MHz
I/O type	COMMON
interleaved burst length	4,8
JESD-30 code	R-PBGA-B78
length	11 mm
memory density	2147483648 bit
Memory IC Type	DDR DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	78
word count	268435456 words
character code	256000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256MX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Encapsulate equivalent code	BGA78,9X13,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.5 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	4,8
Maximum standby current	0.012 A
Maximum slew rate	0.235 mA
Maximum supply voltage (Vsup)	1.575 V
Minimum supply voltage (Vsup)	1.425 V
Nominal supply voltage (Vsup)	1.5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.5 mm

H5TQ2G83DFR-PBJ Preview

2Gb DDR3 SDRAM

Lead-Free&Halogen-Free

(RoHS Compliant)

H5TQ2G83DFR-xxC

H5TQ2G63DFR-xxC

H5TQ2G83DFR-xxI

H5TQ2G63DFR-xxI

H5TQ2G83DFR-xxJ

H5TQ2G63DFR-xxJ

H5TQ2G83DFR-xxL

H5TQ2G63DFR-xxL

* SK Hynix reserves the right to change products or specifications without notice.

Rev. 1.3 / Nov. 2013

Revision History

Revision No.

1.0

1.1

1.2

1.3

History

Official Version Release & Add L/J Part

Delete Comments regarding IDD6TC

& New revised logo (Hynix to SK hynix)

PKG Dimension update (x16)

Commercial Temperature Range update

Draft Date

Apr. 2012

May. 2012

Oct. 2013

Nov. 2013

C ~ 85

C --> 0

C ~ 95

Remark

Add L/J Part support

Page 12/17/24

Rev. 1.3 / Nov. 2013

Description

The H5TQ2G83DFR-xxC, H5TQ2G63DFR-xxC,H5TQ2G83DFR-xxI, H5TQ2G63DFR-xxI, H5TQ2G83DFR-

xxL,H5TQ2G63DFR-xxL,H5TQ2G83DFR-xxJ,H5TQ2G63DFR-xxJ are a

2,147,483,648-bit

CMOS Double Data

Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large

memory density and high bandwidth. SK Hynix 2Gb DDR3 SDRAMs offer fully synchronous operations ref-

erenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on

the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are

sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched

to achieve very high bandwidth.

Device Features and Ordering Information

FEATURES

• VDD=VDDQ=1.5V +/- 0.075V

• Fully differential clock inputs (CK, CK) operation

• Differential Data Strobe (DQS, DQS)

• On chip DLL align DQ, DQS and DQS transition with CK

transition

• DM masks write data-in at the both rising and falling

edges of the data strobe

• All addresses and control inputs except data,

data strobes and data masks latched on the

rising edges of the clock

• Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 12, 13

and 14 supported

• Programmable additive latency 0, CL-1, and CL-2

supported

• Programmable CAS Write latency (CWL) = 5, 6, 7, 8

• Programmable burst length 4/8 with both nibble

sequential and interleave mode

• BL switch on the fly

• 8banks

• Average Refresh Cycle (Tcase

C~ 95

- 7.8 µs at

C ~ 85

- 3.9

µs at 85

C ~ 95

Commercial Temperature(

C ~ 95

Industrial Temperature(

-40

C ~ 95

• JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16)

• Driver strength selected by EMRS

• Dynamic On Die Termination supported

• Asynchronous RESET pin supported

• ZQ calibration supported

• TDQS (Termination Data Strobe) supported (x8 only)

• Write Levelization supported

• 8 bit pre-fetch

* This product in compliance with the RoHS directive.

Rev. 1.3 / Nov. 2013

ORDERING INFORMATION

Part No.

H5TQ2G83DFR-*xxC

H5TQ2G83DFR-*xxI

H5TQ2G83DFR-*xxL

H5TQ2G83DFR-*xxJ

H5TQ2G63DFR-*xxC

H5TQ2G63DFR-*xxI

H5TQ2G63DFR-*xxL

H5TQ2G63DFR-*xxJ

128M x 16

Low Power Consumption

(IDD6 Only)

256M x 8

Low Power Consumption

(IDD6 Only)

Normal Consumption

Configuration

Power Consumption

Normal Consumption

Temperature

Commercial

Industrial

Commercial

Industrial

Commercial

Industrial

Commercial

Industrial

96ball FBGA

78ball FBGA

Package

* xx means Speed Bin Grade

OPERATING FREQUENCY

Speed

Grade

(Marking)

-G7

-H9

-PB

-RD

-TE

Frequency [Mbps]

CL5

667

CL6

800

CL7

1066

CL8

1066

1333

1600

1866

2133

CL9

CL10

CL11

CL12

CL13

CL14

Remark

(CL-tRCD-tRP)

DDR3-1066 7-7-7

DDR3-1333 9-9-9

DDR3-1600 11-11-11

DDR3-1866 13-13-13

DDR3-2133 14-14-14

Rev. 1.3 / Nov. 2013

x8 Package Ball out (Top view): 78ball FBGA Package

VSS

VDDQ

VSSQ

VREFDQ

ODT

VSS

VDD

VSS

VDD

VSS

VDD

VSSQ

DQ2

DQ6

VDDQ

VSS

VDD

BA0

RESET

DQ0

DQS

DQ4

RAS

CAS

BA2

A13

NU/TDQS

DM/TDQS

DQ1

VDD

DQ7

A10/AP

A12/BC

A11

A14

VSS

VSSQ

DQ3

VSS

DQ5

VSS

VDD

VREFCA

BA1

VDD

VDDQ

VSSQ

VDDQ

CKE

VSS

VDD

VSS

VDD

VSS

1 2 3

7 8 9

(Top View: See the balls through the Package)

Populated ball

Ball not populated

Rev. 1.3 / Nov. 2013

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