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NT5CB256M4CN-DG

Description
DDR DRAM, 256MX4, 20ns, CMOS, PBGA78, 0.80 MM PITCH, ROHS COMPLIANT, BGA-78
Categorystorage    storage   
File Size3MB,121 Pages
ManufacturerNanya
Websitehttp://www.nanya.com/cn
Environmental Compliance
Nanya Technology Co., Ltd. aims to become the best DRAM (dynamic random access memory) supplier. It emphasizes customer service and strengthens product R&D and manufacturing through close cooperation with partners, thereby providing customers with comprehensive products and system solutions. In the face of the growing niche DRAM market, Nanya Technology not only provides products ranging from 128Mb to 8Gb, but also continues to expand product diversification. The main application markets include digital TV, set-top box (STB), network communication, tablet computer and other smart electronic systems, automotive and industrial products. At the same time, in order to meet the needs of the rapidly growing mobile and wearable device market, Nanya Technology is more focused on the research and development and manufacturing of low-power memory products. In recent years, Nanya Technology has actively operated in the niche memory market, focusing on the research and development of low-power and customized core product lines. In terms of process progress, it has also introduced 20nm process technology and is committed to the production of DDR4 and LPDDR4 products, hoping to further enhance its overall competitiveness. Nanya Technology will also continue to strengthen its high value-added niche memory products and perfect customer service, enhance core business operating performance, ensure the rights and interests of all shareholders, and create sustainable business value for the company.
Download Datasheet Parametric View All

NT5CB256M4CN-DG Overview

DDR DRAM, 256MX4, 20ns, CMOS, PBGA78, 0.80 MM PITCH, ROHS COMPLIANT, BGA-78

NT5CB256M4CN-DG Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerNanya
Parts packaging codeBGA
package instructionLFBGA, BGA78,9X13,32
Contacts78
Reach Compliance Codecompliant
ECCN codeEAR99
access modeMULTI BANK PAGE BURST
Maximum access time20 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)800 MHz
I/O typeCOMMON
interleaved burst length4,8
JESD-30 codeR-PBGA-B78
length10.5 mm
memory density1073741824 bit
Memory IC TypeDDR DRAM
memory width4
Number of functions1
Number of ports1
Number of terminals78
word count268435456 words
character code256000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature
organize256MX4
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLFBGA
Encapsulate equivalent codeBGA78,9X13,32
Package shapeRECTANGULAR
Package formGRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply1.5 V
Certification statusNot Qualified
refresh cycle8192
Maximum seat height1.39 mm
self refreshYES
Continuous burst length4,8
Maximum supply voltage (Vsup)1.575 V
Minimum supply voltage (Vsup)1.425 V
Nominal supply voltage (Vsup)1.5 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width8 mm

NT5CB256M4CN-DG Preview

Download Datasheet
1Gb DDR3 SDRAM C-Die
NT5CB256M4CN / NT5CB128M8CN
Feature
1.5V ± 0.075V (JEDEC Standard Power Supply)
8 Internal memory banks (BA0- BA2)
Differential clock input (CK,
)
Programmable

Latency: 5, 6, 7, 8, 9, 10
Programmable Additive Latency: 0, CL-1, CL-2
Programmable Sequential / Interleave Burst Type
Programmable Burst Length: 4, 8
8 bit prefetch architecture
Output Driver Impedance Control
Write Leveling
OCD Calibration
Dynamic ODT (Rtt_Nom & Rtt_WR)
Auto Self-Refresh
Self-Refresh Temperature
RoHS Compliance and Halogen free
Packages:
78-Ball BGA for x4 & x8 components
Description
The 1Gb Double-Data-Rate-3 (DDR3) DRAMs is a high-speed CMOS Double Data Rate32 SDRAM containing
1,073,741,824 bits. It is internally configured as an octal-bank DRAM.
The 1Gb chip is organized as 32Mbit x 4 I/O x 8, or 16Mbit x 8 I/O x 8 bank device. These synchronous devices achieve
high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are
synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks
(CK rising and

falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source
synchronous fashion.
These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages.
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