SP9316
Corporation
SIGNAL PROCESSING EXCELLENCE
16–Bit CMOS Multiplying DAC
s
s
s
s
s
s
High Stability with No Laser–Trimming
15–Bit Monotonicity over Temperature
Single Power Supply Operation
Upper/Lower Byte Input Registers
2– and 4–Quadrant Multiplication
60mW Power Dissipation
DESCRIPTION…
The
SP9316
is a 16–bit, monolithic CMOS, multiplying digital-to-analog converter with two 8–bit
input registers for direct microprocessor interface. It offers two– and four–quadrant multiplying
capability with TTL/DTL and CMOS logic compatibility. Operating from a single +15V supply,
power dissipation is less than 60mW. The
SP9316
is packaged in 24-pin ceramic or molded
plastic. Models are available for operation over the commercial (0°C to 70°C) and military (–55°C
to +125°C) temperature ranges. For product screened to MIL–STD–883, please consult the
factory.
BIT: 9 10 11 12 13 14 15 16
4
LSB LATCH
CONTROL
REFERENCE
INPUT
MSB LATCH
CONTROL
19
13
20
5
BIT: 8
3
2
1
24 23 22 21
ANA GND
18
+15V
17
SP9316
15
16
14
5KΩ
I
OUT2
I
OUT1
FEEDBACK
INPUT REGISTER
PRECISION 16-BIT
RESISTOR NETWORK
& SWICHES
INPUT REGISTER
6
7
7
6
8
5
9
4
10 11 12
3
2
1(MSB)
Corporation
181
SIGNAL PROCESSING EXCELLENCE
ABSOLUTE MAXIMUM RATINGS
(T
A
=25°C unless otherwise noted)
These are stress ratings only and functional operation of the device
at these or any other above those indicated in the operation
sections of the specifications below is not implied. Exposure to
absolute maximum rating conditions for extended periods of time
may affect reliability.
V
DD
to GND ................................................................. -–0.3V, +17V
Digital Input Voltage to GND ............................... -–0.3V ,V
DD
+0.3V
V
REF
or V
RFB
to GND ................................................................
±25V
Output Voltage (Pin 15, Pin 16) ........................... –0.3V, V
DD
+0.3V
Power Dissipation (Any Package) to +75°C ........................ 450mW
Derates above 75°C by ...................................................... 6mW/°C
Dice Junction Temperature ................................................. +150°C
Storage Temperature .......................................... -–65°C to +150°C
SPECIFICATIONS
(T
A
=25°C; V
DD
=+15V, V
REF
= +10V; I
O1
= AGND = GND = 0V; unipolar unless otherwise noted.)
PARAMETER
MIN.
TYP.
STATIC PERFORMANCE
Resolution
16
Integral Non-Linearity
C-4
B-4
Differential Non-Linearity
C-4
B-4
Offset Error
Gain Error
0.1
AC PERFORMANCE CHARACTERISTICS
Propagation Delay
300
Current Settling Time
To 0.01% FSR (strobed)
2.0
To 0.00076% FSR (strobed)
3.0
Output Capacitance
C
O1
170
C
O2
30
C
O3
80
C
O4
100
Glitch Energy
250
Multiplying Feedthrough Error
3.0
0.3
STABILITY
All Grades:
Gain Error TC
±1.0
Offset
Integral Non-Linearity TC
±0.1
Monotonicity Guaranteed
C-4
14
B-4
14
Power Supply Rejection
LONG-TERM STABILITY
Differential Non-linearity
Offset
Gain
REFERENCE INPUT
Input Impedance
2.5
Voltage Range
–10
SWITCHING CHARACTERISTICS
Strobe Width
80
Data Setup Time
80
Data Hold Time
40
MAX.
UNIT
Bits
CONDITIONS
±0.006
±0.006
±0.006
±0.006
60
0.2
Note 5
%FSR
%FSR
Note 7
%FSR
%FSR
µV
%FSR
ns
µs
µs
pF
pF
pF
pF
nV-s
mV
P-P
mV
P-P
Note 3
Note 4
Note 9
Major code settling times
Digital input V
IH
Digital input V
IH
Digital input V
IL
Digital input V
IL
Note 10
Note 11
Note 12
Note 4
Note 6
Note 5
±4.0
±1.0
±1.0
±1.0
ppm/°C
ppm/°C
ppm/°C
ppm/°C
Bits
Bits
%/%
ppm/°C
ppm/°C
ppm/°C
±0.0001
1
±0.5
±1
5.0
±0.002
V
DD
= 14.0V to 16.0V
7.5
+10
KΩ
Volts
ns
ns
ns
60
70
20
182
Corporation
SIGNAL PROCESSING EXCELLENCE
SPECIFICATIONS
(continued)
(T
A
=25°C; V
DD
=+15V, V
REF
= +10V; I
O1
= AGND = GND = 0V; unipolar unless otherwise noted.)
PARAMETER
MIN.
TYP.
MAX.
DIGITAL INPUTS
Logic Levels
V
IH
2.4
V
DD
V
IL
-0.3
0.8
Input Current
±1.0
±10.0
Input Capacitance
8
Coding
2-Quadrant Unipolar
Binary
4-Quadrant Bipolar
Offset Binary
ANALOG OUTPUT
Small Signal -3dB Bandwidth
1
Output Capacitance
C
OUT1
90
C
OUT2
70
POWER REQUIREMENTS
Supply Current
2.0
4.0
Voltage Range V
DD
+5
+15
+16
Power Dissipation
60
ENVIRONMENTAL AND MECHANICAL
Operating Temperature
Commercial
0
+70
Military
-55
+125
Storage Temperature
-65
+150
Package
Commercial
24–pin Plastic DIP
Military
24–pin CerDIP
UNIT
CONDITIONS
Volts
Volts
µA
pF
Note 1
Note 2
MHz
pF
pF
mA
Volts
mW
DIG IN = V
IL
or V
IH
DIG IN = V
IL
or V
IH
°C
°C
°C
Notes and Cautions:
1.
Logic inputs are MOS gates. I
IN
typically is less than 1nA @ 25°C.
2.
Guaranteed by design, but not production tested.
3.
Unipolar: Using the internal R
FEEDBACK
with nulled external amplifier in a constant 25°C ambient (offset doubles every 10°C).
4.
Using internal feedback resistor.
5.
Integral Linearity, for this product, is measured as the arithmetic mean value of the magnitudes of the greatest positive deviation
and the greatest negative deviation from the theoretical value for any given input combination.
Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two adjacent digital input codes.
6.
The
SP9316
series is designed to be used only in those applications where the current output is virtual ground; i.e. the summing
junction of an op amp in the inverting mode. The internal feedback resistor must be used to achieve temperature tracking. See
applications information for recommended circuit configurations.
7.
For military temperature range product, screened to MIL-STD-883C, please consult the factory.
8.
Sample tested only to ensure compliance.
9.
I
O1
load R
L
= 100Ω, C
EXT
= 13pF; all data inputs 0V to V
DD
or V
DD
to 0V; from 50% digital input change to 90% of final analog
output.
10.
V
REF
= 0V, DAC register alternatively loaded with all 0’s and all 1’s.
11.
Measured at output I
O1
; V
REF
= 20V
P-P
; F = 10kHz sinewave.
12.
Measured at output I
O1
; V
REF
= 20V
P-P
; F = 1kHz sinewave.
0.000
Parameter Change (% FSR)
0.002
0.004
0.006
0.008
0.010
0
1
2
3
4
5
Warm–Up Time(Minutes)
Error in LSB's
1.0
0.5
Typical @ 25°C
and +15V nominal
-10
-5
0
V
REF
(Volts)
+5
+ 10
Corporation
183
SIGNAL PROCESSING EXCELLENCE
PIN ASSIGNMENTS
Pin 1 — DB
12
— Data Bit 12.
Pin 2 — DB
11
— Data Bit 11.
Pin 3 — DB
10
— Data Bit 10.
Pin 4 — DB
9
— Data Bit 9.
Pin 5 — DB
8
— Data Bit 8.
Pin 6 — DB
7
— Data Bit 7.
Pin 7 — DB
6
— Data Bit 6.
Pin 8 — DB
5
— Data Bit 5.
Pin 9 — DB
4
— Data Bit 4.
Pin 10 — DB
3
— Data Bit 3.
Pin 11 — DB
2
— Data Bit 2.
Pin 12 — DB
1
— Data Bit 1 (MSB).
Pin 13 — V
REF
In — Voltage Reference Input.
Pin 14 — R
FB
— Feedback Resistor.
Pin 15 — I
OUT2
— Current Output.
Pin 16 — I
OUT1
— Inverted Current Output.
Pin 17 — VDD — +15V Power Supply.
Pin 18 — GND — Analog GND.
Pin 19 — LSB LATCH — LSB Latch control.
Level–triggered. Data is latched with strobe at
logic 0; logic 1 allows data to update DAC
directly.
Pin 20 — MSB LATCH — MSB Latch control.
Level–triggered. Logic 0 strobes data into latch;
logic 1 allows data to update DAC directly.
Pin 21 — DB
16
— Data Bit 16 (LSB) .
Pin 22 — DB
15
— Data Bit 15.
Pin 23 — DB
14
— Data Bit 14.
Pin 24 — DB
13
— Data Bit 13.
FEATURES…
The
SP9316
is a 16-bit, monolithic CMOS,
multiplying digital-to-analog converter with two
8-bit input registers for direct microprocessor
interface. It offers two– and four–quadrant mul-
tiplying capability with TTL/DTL and CMOS
logic compatibility. It is ideally suited for Auto-
mated Test Equipment, medical instrumenta-
tion and high–energy physics applications. Op-
erating from a single +15V supply, power dissi-
pation is less than 60mW. High accuracy and
monotonicity are achieved without laser–trim-
ming through the use of a highly accurate, low–
TCR thin–film resistor process. A unique digital
decoding technique of the 4 MSB’s results in
excellent linearity and stability over both time
and temperature. The
SP9316
is packaged in
hermetic 24-pin ceramic or molded plastic.
Models are available for operation over the
commercial (0°C to 70°C) and military (–55°C
to +125°C) temperature ranges. For product
screened to MIL–STD–883, please consult the
factory.
400Ω
V
REF
13
17
GND 18
BIT 1 (MSB)
R
FB
DIGITAL
INPUT
SP9316
I
OUT1
16
_
A
I
OUT2
15
+
All "ones":
V
OUT
= –V
REF
+ 1LSB
V
OUT
14
R
OS
+15V
0.01µF + 1µF
BIT 16 (LSB)
MSB LATCH
LSB LATCH
NOTE:
To maintain specified linearity, the external amplifier (A)
must be nulled. Apply an "all zeroes" digital input and adjust
R
OS
for V
OUT
= 0±1mV.
Figure 1. Unipolar Operation
USING THE SP9316
General Configuration
The
SP9316
can be configured for unipolar
voltage operation (2-quadrant multiplication)
or bipolar voltage operation (4-quadrant multi-
plication.) Coding is binary and offset binary
respectively. In bipolar operation both the ref-
erence signal and the number represented by the
digital input applied to the
SP9316
may be of
either positive or negative polarity.
184
Corporation
SIGNAL PROCESSING EXCELLENCE
Individual latch controls are provided for the
high and low bytes which may be tied together
for a single 16-bit word update. The data is
latched with the strobe at logic 0. The latches are
level–triggered and can be made transparent by
tying them to logic 1. However, use of the
latches is recommended in most applications as
they significantly reduce data bit skew, which
affects the glitch performance.
Layout, Grounding and Guarding
16-bit system performance can be maintained
with suitable attention paid to the layout, ground-
ing and guarding techniques employed. All
grounds should be of as low resistance as pos-
sible. Analog and digital grounds should be
individually star-pointed and tied together as
close as possible to the
SP9316.
Good layout
techniques dictate that the high–speed digital
inputs should be kept separate from low–level
analog outputs. The DAC output and op amp
input are high impedance and so are sensitive to
interference from the digital input lines. Careful
pinout design of the
SP9316
has reduced this
problem to a minimum, but guarding of these
points should be considered. Figures 3 and 4
detail the low impedance guard track layout.
Amplifier Selection
The
SP9316
allows the designer to obtain the
optimum performance for each application. Se-
lection of the correct operational amplifier, and
the layout of the associated components are
critical to the success of the design. To obtain
the optimum linearity performance, the amplifi-
ers must have an open loop gain in excess of
100,000 or 100dB. Care should be taken to
400Ω
V
REF
13
17
GND 18
BIT 1 (MSB)
R
FB
DIGITAL
INPUT
SP9316
I
OUT1
16
_
R
BIT 16 (LSB)
MSB LATCH
LSB LATCH
A
1
I
OUT2
15
+
V
O1
+
All "ones":
V
OUT
= –V
REF
+ 1LSB
_
A
2
V
OUT
14
R
OS1
R for ±5V FS output
2R for ±10V FS output
R
OS2
+15V
0.01µF + 1µF
2R
Binary Input
111…111
100…001
100…000
011…111
000…001
000…000
Analog Output
-V (1-2 )
-V ( +2 )
-V ( )
N
REF
-N
REF
REF
-V ( -2 )
-V (2 )
0
-N
REF
-N
REF
Table 1. Unipolar Transfer Function
ensure that the summing junction is as close to
analog ground as possible. Most applications
demand that the input offset be kept below
100µV. To maintain accuracy over temperature,
the amplifiers should have low bias currents and
offset voltage temperature coefficients.
In bipolar applications, attention must be paid to
the choice of resistors R and 2R (see
figure 2).
As the analog voltage output increases from
zero to full-scale, the power dissipated by the
feedback resistor increases and the resistor heats
up. This causes a small change in the resistance
value which could lead to an alteration to the
transfer function, which may be seen as integral
linearity errors. The internal resistor network
has been designed using ultra-stable thin-film
nichrome. It is important that the temperature
coefficient of the external resistors match those
in the DAC as closely as possible. Resistors
with a temperature coefficient of 10ppm/°C or
better should be used.
LONG TERM DRIFT
When measuring the stability of the
SP9316,
great care should be taken to ensure that the drift
of the measurement instruments can be sepa-
Offset Binary Input
111…111
100…001
100…000
011…111
000…001
000…000
Analog Output
-V (1-2 )
-V (2 )
0
V (2 )
V (1-2 )
V
-(N-1)
REF
-(N-1)
REF
-(N-1)
REF
-(N-1)
REF
REF
NOTE:
To maintain specified linearity, the external amplifiers (A
1
and A
2
)
must be nulled. With a digital input of 10…0 and V
REF
set to zero —
1) set R
OS1
for V
O1
= 0V;
2) set R
OS2
for V
OUT
= 0V;
3) set V
REF
to +10V and adjust R
B
for V
OUT
= 0V
Figure 2. Bipolar Operation
Table 2. Bipolar Transfer Function
Corporation
185
SIGNAL PROCESSING EXCELLENCE
Embedded System
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