UPD45D128442G5-C12-9LG datasheet, PDF

Datasheet> All Categories > storage> storage> UPD45D128442G5-C12-9LG

UPD45D128442G5-C12-9LG: DescriptionDDR DRAM, 32MX4, 1.5ns, MOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66; Categorystorage storage; File Size642KB，80 Pages; ManufacturerELPIDA; Websitehttp://www.elpida.com/en

Download Datasheet Parametric Compare View All

UPD45D128442G5-C12-9LG Overview

DDR DRAM, 32MX4, 1.5ns, MOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66

UPD45D128442G5-C12-9LG Parametric

Parameter Name	Attribute value
Maker	ELPIDA
Parts packaging code	TSOP2
package instruction	TSOP2,
Contacts	66
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	1.5 ns
JESD-30 code	R-PDSO-G66
length	22.22 mm
memory density	134217728 bit
Memory IC Type	DDR DRAM
memory width	4
Number of functions	1
Number of ports	1
Number of terminals	66
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32MX4
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	MOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
width	10.16 mm

Preview

Download Datasheet

View All

PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

PD45D128442, 45D128842, 45D128164

128 M-bit Synchronous DRAM with Double Data Rate

(4-bank, SSTL_2)

Description

The

PD45D128442, 45D128842, 45D128164 are high-speed 134,217,728 bits synchronous dynamic random-

access memories, organized as 8,388,608x4x4, 4194,304x8x4, 2,097,152x16x4 (word x bit x bank), respectively.

The synchronous DRAMs use Double Data Rate (DDR) where data bandwidth is twice of regular synchronous

DRAM.

The synchronous DRAM is compatible with SSTL_2 (Stub Series terminated Logic for 2.5 V).

The synchronous DRAM is packaged in 66-pin Plastic TSOP (II).

Features

•

Fully Synchronous Dynamic RAM with all input signals except DM, DQS and DQ referenced to a positive clock edge

•

Double Data Rate interface

Differential CLK (/CLK) input

Data inputs and DM are synchronized with both edges of DQS

Data outputs and DQS are synchronized with a cross point of CLK and /CLK

•

Quad internal banks operation

•

Possible to assert random column address in every clock cycle

•

Programmable Mode register set

/CAS latency (2, 2.5)

Burst length (2, 4, 8)

Wrap sequence (Sequential / Interleave)

•

Automatic precharge and controlled precharge

•

Auto refresh (CBR refresh) and self refresh

•

x4, x8, x16 organization

•

Byte write control (x4, x8) by DM

•

Byte write control (x16) by LDM and UDM

•

2.5 V

0.125 V Power supply for Vcc

•

2.5 V

0.125 V Power supply for VccQ

•

Maximum clock frequency up to 133 MHz

•

SSTL_2 compatible with all signals

•

4,096 refresh cycles/64 ms

•

66-pin Plastic TSOP (II) (400 mil)

•

Burst termination by Precharge command and Burst stop command

The information in this document is subject to change without notice.

Document No. M13852EJ1V1DS00 (1st edition)

Date Published December 1998 NS CP(K)

Printed in Japan

The mark

•

shows major revised points.

1998

UPD45D128442G5-C12-9LG Related Products

	UPD45D128442G5-C12-9LG	UPD45D128164G5-C12-9LG	UPD45D128842G5-C12-9LG	UPD45D128842G5-C10-9LG	UPD45D128442G5-C10-9LG	UPD45D128164G5-C10-9LG
Description	DDR DRAM, 32MX4, 1.5ns, MOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66	DDR DRAM, 8MX16, 1.5ns, MOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66	DDR DRAM, 16MX8, 1.5ns, MOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66	DDR DRAM, 16MX8, 1.5ns, MOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66	DDR DRAM, 32MX4, 1.5ns, MOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66	DDR DRAM, 8MX16, 1.5ns, MOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66
Parts packaging code	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2
package instruction	TSOP2,	TSOP2,	TSOP2,	TSOP2,	TSOP2,	TSOP2,
Contacts	66	66	66	66	66	66
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	1.5 ns	1.5 ns	1.5 ns	1.5 ns	1.5 ns	1.5 ns
JESD-30 code	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66	R-PDSO-G66
length	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm
memory density	134217728 bit	134217728 bit	134217728 bit	134217728 bit	134217728 bit	134217728 bit
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	4	16	8	8	4	16
Number of functions	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1
Number of terminals	66	66	66	66	66	66
word count	33554432 words	8388608 words	16777216 words	16777216 words	33554432 words	8388608 words
character code	32000000	8000000	16000000	16000000	32000000	8000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	32MX4	8MX16	16MX8	16MX8	32MX4	8MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V	2.625 V
Minimum supply voltage (Vsup)	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V	2.375 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	YES	YES	YES	YES	YES	YES
technology	MOS	MOS	MOS	MOS	MOS	MOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
width	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm
Maker	ELPIDA	-	ELPIDA	ELPIDA	ELPIDA	ELPIDA

Recommended Resources

Analysis of commonly used anti-interference technologies

Broadband high frequency amplifier circuit

Typical gate drive circuit of GTO

Precision absolute converter circuit with wide dynamic range

Example circuit diagram of switching power supply using μPC1943,1944

555 carrier signal processing and control circuit

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components