DATASHEET
REAL-TIME CLOCK WITH SERIAL I
2
C INTERFACE
General Description
The IDT1339 serial real-time clock (RTC) is a low-power
clock/date device with two programmable time-of-day
alarms and a programmable square-wave output. Address
and data are transferred serially through an I
2
C bus. The
clock/date provides seconds, minutes, hours, day, date,
month, and year information. The date at the end of the
month is automatically adjusted for months with fewer than
31 days, including corrections for leap year. The clock
operates in either the 24-hour or 12-hour format with
AM/PM indicator. The IDT1339 has a built-in power-sense
circuit that detects power failures and automatically
switches to the backup supply, maintaining time, date, and
alarm operation.
IDT1339
Features
•
Real-Time Clock (RTC) counts seconds, minutes, hours,
day, date, month, and year with leap-year compensation
valid up to 2100
•
Packaged in 8-pin MSOP, 8-pin SOIC, or 16-pin SOIC
(surface-mount package with an integrated crystal)
Applications
•
Handhelds (GPS, POS terminals)
•
Consumer Electronics (Set-Top Box, Digital Recording,
Network Applications)
•
•
•
•
•
•
•
•
Fast mode I
2
C Serial interface
Two time-of-day alarms
Programmable square-wave output
Oscillator stop flag
Automatic power-fail detect and switch circuitry
Trickle-charge capability
Industrial temperature range (-40 to +85°C)
Underwriters Laboratory (UL) recognized
•
•
•
•
Office (Fax/Printers, Copiers)
Medical (Glucometer, Medicine Dispensers)
Telecomm (Routers, Switches, Servers)
Other (Thermostats, Vending Machines, Modems, Utility
Meters)
Block Diagram
Crystal inside package
for 16-pin SOIC ONLY
1 Hz/4.096 kHz/
8.192 kHz/32.768 kHz
X1
32.768 kHz
Oscillator and
Divider
MUX/
Buffer
SQW/INT
X2
GND
VCC
Trickle
Charger
Power
Control
Control
Logic
Clock,
Calendar
Counter
V
BACKUP
SDA
I
2
C
Interface
Trickle
Charger
Byte
SCL
1 Byte
Control
7 Bytes
Buffer
7 Bytes
Alarm
1 Byte
Status
IDT®
REAL-TIME CLOCK WITH SERIAL I
2
C INTERFACE
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IDT1339
REV S 031014
IDT1339
REAL-TIME CLOCK WITH SERIAL I
2
C INTERFACE
RTC
Pin Assignment
(8-pin MSOP/8-pin SOIC)
X1
X2
V
BACKUP
GND
1
2
3
4
8
VCC
SQW/INT
SCL
SDA
Pin Assignment
(16-pin SOIC)
SCL
SQW/INT
VCC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
16
15
14
SDA
GND
V
BACKUP
NC
NC
NC
NC
NC
IDT
1339
7
6
5
IDT
1339C
13
12
11
10
9
Pin Descriptions
Pin
Number
MSOP SOIC
1
2
—
—
Pin
Name
X1
X2
Pin Description/Function
Connections for standard 32.768 kHz quartz crystal. The internal oscillator circuitry is
designed for operation with a crystal having a specified load capacitance (CL) of 7 pF. An
external 32.768 kHz oscillator can also drive the IDT1339. In this configuration, the X1 pin
is connected to the external oscillator signal and the X2 pin is left floating.
Backup supply input. Supply voltage must be held between 1.3 V and 3.7 V for proper
operation. This pin can be connected to a primary cell, such as a lithium button cell.
Additionally, this pin can be connected to a rechargeable cell or a super cap that can be
charged using the trickle charger circuit. Diodes placed in series between the backup
source and the VBAT pin may prevent proper operation. If a backup supply is not required,
VBAT must be connected to ground. UL recognized to ensure against reverse charged
current when used with a lithium cell.
Connect to ground. DC power is provided to the device on these pins.
Serial data input/output. SDA is the input/output pin for the I
2
C serial interface. The SDA pin
is an open-drain output and requires an external pull-up resistor (2 k typical).
Serial clock input. SCL is used to synchronize data movement on the serial interface. It is an
open-drain output and requires an external pull-up resistor (2 k typical).
3
14
V
BACKUP
4
5
6
7
15
16
1
2
GND
SDA
SCL
SQW/INT Square-Wave/Interrupt output. Programmable square-wave or interrupt output signal. The
SQW/INT pin is an open-drain output and requires an external pull-up resistor (10 k
typical).
V
CC
8
—
3
4 - 13
Primary power supply. When voltage is applied within normal limits, the device is fully
accessible and data can be written and read.
No connect. These pins are unused and must be connected to ground.
NC
IDT®
REAL-TIME CLOCK WITH SERIAL I
2
C INTERFACE
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IDT1339
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IDT1339
REAL-TIME CLOCK WITH SERIAL I
2
C INTERFACE
RTC
Typical Operating Circuit
V
CC
R
PU
2k
CPU
V
CC
R
PU
2k
1
CRYSTAL
2
V
CC
8
X1
6
X2
V
CC
SQW/INT
7
3
10k
SCL
SDA
5
IDT1339
GND
4
V
BACKUP
+
-
Detailed Description
The following sections discuss in detail the Oscillator block,
Power Control block, Clock/Calendar Register, Alarms,
trickle Charger, and Serial I
2
C block.
Oscillator Block
Selection of the right crystal, correct load capacitance and
careful PCB layout are important for a stable crystal
oscillator. Due to the optimization for the lowest possible
current in the design for these oscillators, losses caused by
parasitic currents can have a significant impact on the
overall oscillator performance. Extra care needs to be taken
to maintain a certain quality and cleanliness of the PCB.
Crystal Selection
The key parameters when selecting a 32 kHz crystal to work
with IDT1339 RTC are:
In the above figure, X1 and X2 are the crystal pins of our
device. Cin1 and Cin2 are the internal capacitors which
include the X1 and X2 pin capacitance. Cex1 and Cex2 are
the external capacitors that are needed to tune the crystal
frequency. Ct1 and Ct2 are the PCB trace capacitances
between the crystal and the device pins. CS is the shunt
capacitance of the crystal (as specified in the crystal
manufacturer's datasheet or measured using a network
analyzer).
Note:
IDT1339CSRI integrates a standard 32.768 kHz
(±20ppm) crystal in the package and contributes an
additional frequency error of 10ppm at nominal
V
CC
(+3.3 V)
and T
A
=
+25°C.
•
Recommended Load Capacitance
•
Crystal Effective Series Resistance (ESR)
•
Frequency Tolerance
Effective Load Capacitance
Please see diagram below for effective load capacitance
calculation. The effective load capacitance (CL) should
match the recommended load capacitance of the crystal in
order for the crystal to oscillate at its specified parallel
resonant frequency with 0ppm frequency error.
IDT®
REAL-TIME CLOCK WITH SERIAL I
2
C INTERFACE
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REAL-TIME CLOCK WITH SERIAL I
2
C INTERFACE
RTC
ESR (Effective Series Resistance)
Choose the crystal with lower ESR. A low ESR helps the
crystal to start up and stabilize to the correct output
frequency faster compared to high ESR crystals.
PCB Layout
Frequency Tolerance
The frequency tolerance for 32 KHz crystals should be
specified at nominal temperature (+25°C) on the crystal
manufacturer datasheet. The crystals used with IDT1338
typically have a frequency tolerance of ±20ppm at +25°C.
Specifications for a typical 32 kHz crystal used with our
device are shown in the table below.
1339
PCB Assembly, Soldering and Cleaning
Parameter
Nominal Freq.
Series Resistance
Load Capacitance
Symbol
f
O
ESR
C
L
Min
Typ
32.768
Max Units
kHz
50
k
pF
7
PCB Design Consideration
•
Signal traces between IDT device pins and the crystal
must be kept as short as possible. This minimizes
parasitic capacitance and sensitivity to crosstalk and
EMI. Note that the trace capacitances play a role in the
effective crystal load capacitance calculation.
•
Data lines and frequently switching signal lines should be
routed as far away from the crystal connections as
possible. Crosstalk from these signals may disturb the
oscillator signal.
Board-assembly production process and assembly quality
can affect the performance of the 32 kHz oscillator.
Depending on the flux material used, the soldering process
can leave critical residues on the PCB surface. High
humidity and fast temperature cycles that cause humidity
condensation on the printed circuit board can create
process residuals. These process residuals cause the
insulation of the sensitive oscillator signal lines towards
each other and neighboring signals on the PCB to decrease.
High humidity can lead to moisture condensation on the
surface of the PCB and, together with process residuals,
reduce the surface resistivity of the board. Flux residuals on
the board can cause leakage current paths, especially in
humid environments. Thorough PCB cleaning is therefore
highly recommended in order to achieve maximum
performance by removing flux residuals from the board after
assembly. In general, reduction of losses in the oscillator
circuit leads to better safety margin and reliability.
•
Reduce the parasitic capacitance between X1 and X2
signals by routing them as far apart as possible.
Power Control
The power-control function is provided by a precise,
temperature-compensated voltage reference and a
comparator circuit that monitors the
V
CC
level. The device is
fully accessible and data can be written and read when
V
CC
is greater than V
PF
. However, when
V
CC
falls below V
PF
, the
internal clock registers are blocked from any access. If V
PF
is less than V
BACKUP
, the device power is switched from
V
CC
to V
BACKUP
when
V
CC
drops below V
PF
. If V
PF
is greater than
V
BACKUP
, the device power is switched from
V
CC
to V
BACKUP
when
V
CC
drops below V
BACKUP
. The registers are
maintained from the V
BACKUP
source until
V
CC
is returned to
nominal levels (Table 1). After
V
CC
returns above V
PF
, read
and write access is allowed after t
REC
(see the
“Power-Up/Down Timing” diagram).
•
The oscillation loop current flows between the crystal and
the load capacitors. This signal path (crystal to CL1 to
CL2 to crystal) should be kept as short as possible and
ideally be symmetric. The ground connections for both
capacitors should be as close together as possible.
Never route the ground connection between the
capacitors all around the crystal, because this long
ground trace is sensitive to crosstalk and EMI.
•
To reduce the radiation / coupling from oscillator circuit,
an isolated ground island on the GND layer could be
made. This ground island can be connected at one point
to the GND layer. This helps to keep noise generated by
the oscillator circuit locally on this separated island. The
ground connections for the load capacitors and the
oscillator should be connected to this island.
IDT®
REAL-TIME CLOCK WITH SERIAL I
2
C INTERFACE
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REAL-TIME CLOCK WITH SERIAL I
2
C INTERFACE
RTC
Table 1. Power Control
Supply Condition
V
CC
< V
PF
, V
CC
<
V
BACKUP
V
CC
< V
PF
, V
CC
>
V
BACKUP
V
CC
> V
PF
, V
CC
<
V
BACKUP
V
CC
> V
PF
, V
CC
>
V
BACKUP
Read/Write
Access
No
No
Yes
Yes
Powered
By
V
BACKUP
V
CC
V
CC
V
CC
Power-up/down Timing
Table 2. Power-up/down Characteristics
Ambient Temperature -40 to +85C
Parameter
Recovery at Power-up
V
CC
Fall Time; V
PF(MAX)
to V
PF(MIN)
V
CC
Rise Time; V
PF(MIN)
to V
PF(MAX)
Symbol
t
REC
t
VCCF
t
VCCR
Conditions
(see note 1)
(see note 2)
Min.
3
0
Typ.
Max.
2
Units
ms
ms
µs
Note 1:
This delay applies only if the oscillator is running. If the oscillator is disabled or stopped, no power-up delay
occurs.
Note 2:
Measured at typ VBAT level.
IDT®
REAL-TIME CLOCK WITH SERIAL I
2
C INTERFACE
5
IDT1339
REV S 031014
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