ADVANCE INFORMATION
Am29LV641GH/L / Am29LV640GU
64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only
Uniform Sector Flash Memory with VersatileI/O Control
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
■
Single power supply operation
— 2.7 to 3.6 volt read, erase, and program operations
■
SecSi (Secured Silicon) Sector region
— 128-word sector for permanent, secure identification
through an 8-word random Electronic Serial Number
— May be programmed and locked at the factory or by
the customer
— Accessible through a command sequence
■
VersatileI/O control
— Device generates data output voltages and tolerates
data input voltages as determined by the voltage on
the V
IO
pin
■
Manufactured on 0.17 µm process technology
■
Flexible sector architecture
— One hundred twenty-eight 32 Kword sectors
■
Compatibility with JEDEC standards
— Pinout and software compatible with single-power
supply Flash standard
■
Package options
— 48-pin TSOP and Reverse TSOP (LV641GH/L only)
— 63-ball Fine-pitch BGA (LV640GU only)
— 64-ball Fortified BGA (LV640GU only)
■
Minimum 1 million erase cycle guarantee per sector
■
20-year data retention at 125°C
■
Ultra low power consumption (typical values at 3.0 V,
5 MHz)
— 9 mA typical active read current
— 26 mA typical erase/program current
— 200 nA typical standby mode current
■
Program and erase performance (V
HH
not applied to
the ACC input pin)
— Word program time: 7 µs typical
— Sector erase time: 0.6 s typical for each 32 Kword
sector
SOFTWARE AND HARDWARE FEATURES
■
Hardware features
—
Hardware reset input (RESET#):
resets device for
new operation
—
WP# input:
protects first or last 32 Kword sector
regardless of sector protection settings
(LV641GH/L only)
—
ACC input:
Accelerates programming time for higher
throughput during system production
■
Software features
—
Program Suspend & Resume:
read other sectors
before programming operation is completed
—
Sector Group Protection:
V
CC
-level method of
preventing program or erase operations within a
sector
—
Temporary Sector Group Unprotect:
V
ID
-level method
of changing in previously locked sectors
—
CFI (Common Flash Interface) compliant:
allows host
system to identify and accommodate multiple flash
devices
—
Erase Suspend/Erase Resume:
read/program other
sectors before an erase operation is complete
—
Data# Polling
and
toggle bits
provide erase and
programming operation status
—
Unlock Bypass Program
command reduces overall
multiple-word programming time
PERFORMANCE CHARCTERISTICS
■
High performance
— Access time ratings as fast as 70 ns
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you
evaluate this product. Do not design in this product without contacting the factory. AMD reserves the right to change or discontinue work
on this proposed product without notice.
Publication#
25295
Rev:
A
Amendment/1
Issue Date: August 28, 2002
Refer to AMD’s Website (www.amd.com) for the latest information.
A D V A N C E
I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29LV641GH/L / Am29LV640GU are 64 Mbit,
3.0 volt (2.7 V to 3.6 V) single power supply flash
memory devices organized as 4,194,304 words. Data
appears on DQ15–DQ0. These devices are designed
to be programmed in-system with the standard system
3.0 volt V
CC
supply. A 12.0 volt V
PP
is not required for
program or erase operations. The device can also be
programmed in standard EPROM programmers.
Access times of 70, 90, and 100 ns are available for
applications where V
IO
≥
V
CC
. Access times of 90 and
100 ns are available for applications where V
IO
< V
CC
.
The Am29LV641GH/L is offered in 48-pin TSOP and
reverse TSOP packages. The Am29LV640GU is of-
fered in a 63-ball Fine-pitch BGA package and a
64-ball Fortified BGA. To eliminate bus contention
each device has separate chip enable (CE#), write en-
able (WE#) and output enable (OE#) controls.
Each device requires only a
single 3.0 volt power
supply
(2.7 V to 3.6 V) for both read and write func-
tions. Internally generated and regulated voltages are
provided for the program and erase operations.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timing. Register con-
tents serve as inputs to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already pro-
grammed) before executing the erase operation. Dur-
ing erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The
VersatileI/O™
(V
IO
) control allows the host sys-
tem to set the voltage levels that the device generates
at its data outputs and the voltages tolerated at its
data inputs to the same voltage level that is asserted
on the V
IO
pin. This allows the device to operate in 1.8
V or 3 V system environment as required.
The host system can detect whether a program or
erase operation is complete by reading the DQ7
(Data# Polling) or DQ6 (toggle)
status bits.
After a
program or erase cycle has been completed, the de-
2
vice is ready to read array data or accept another
command.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The
Erase Suspend/Erase Resume
feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved. The
Program Suspend/Program
Resume
feature enables the host system to pause a
program operation in a given sector to read any other
sector and then complete the program operation.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to
the system reset circuitry. A system reset would thus
also reset the device, enabling the system micropro-
cessor to read boot-up firmware from the Flash mem-
ory device.
The device offers a
standby mode
as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
The
SecSi (Secured Silicon) Sector
provides an
minimum 128-word area for code or data that can be
permanently protected. Once this sector is protected,
no further programming or erasing within the sector
can occur.
The
Write Protect (WP#)
feature protects the first or
last sector by asserting a logic low on the WP# pin.
The protected sector will still be protected even during
accelerated programming. (Am29LV641GH/L only)
The
accelerated program (ACC)
feature allows the
system to program the device at a much faster rate.
When ACC is pulled high to V
HH
, the device enters the
Unlock Bypass mode, enabling the user to reduce the
time needed to do the program operation. This feature
is intended to increase factory throughput during sys-
tem production, but may also be used in the field if de-
sired.(Am29LV641GH/L only)
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.
August 28, 2002
Am29LV641GH/L / Am29LV640GU
A D V A N C E
I N F O R M A T I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Special Package Handling Instructions .................................... 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations .....................................................10
DQ7: Data# Polling ................................................................. 29
Figure 5. Data# Polling Algorithm .................................................. 29
DQ6: Toggle Bit I .................................................................... 29
Figure 6. Toggle Bit Algorithm........................................................ 30
DQ2: Toggle Bit II ................................................................... 31
Reading Toggle Bits DQ6/DQ2 ............................................... 31
DQ5: Exceeded Timing Limits ................................................ 31
DQ3: Sector Erase Timer ....................................................... 31
Table 11. Write Operation Status ................................................... 32
VersatileI/O (V
IO
) Control .................................................... 10
Requirements for Reading Array Data ................................... 10
Writing Commands/Command Sequences ............................ 11
Accelerated Program Operation ......................................................11
Autoselect Functions .......................................................................11
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 33
Figure 7. Maximum Negative Overshoot Waveform ..................... 33
Figure 8. Maximum Positive Overshoot Waveform....................... 33
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 33
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 9. I
CC1
Current vs. Time (Showing
Active and Automatic Sleep Currents) ........................................... 35
Figure 10. Typical I
CC1
vs. Frequency ............................................ 35
Standby Mode ........................................................................ 11
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 12
Table 2. Sector Address Table ........................................................12
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 11. Test Setup.................................................................... 36
Table 12. Test Specifications ......................................................... 36
Autoselect Mode ..................................................................... 16
Table 3. Am29LV641GH/L / Am29LV640GU Autoselect Codes,
(High Voltage Method) ...................................................................16
Key to Switching Waveforms. . . . . . . . . . . . . . . . 36
Figure 12. Input Waveforms and
Measurement Levels...................................................................... 36
Sector Group Protection and Unprotection ............................. 17
Table 4. Sector Group Protection/Unprotection Address Table .....17
Write Protect (WP#) ................................................................ 18
Temporary Sector Group Unprotect ....................................... 18
Figure 1. Temporary Sector Group Unprotect Operation................ 18
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 19
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
Read-Only Operations ........................................................... 37
Figure 13. Read Operation Timings ............................................... 37
Hardware Reset (RESET#) .................................................... 38
Figure 14. Reset Timings............................................................... 38
SecSi (Secured Silicon) Sector Flash Memory Region ....... 20
Table 5. SecSi Sector Contents ......................................................20
Erase and Program Operations .............................................. 39
Figure 15. Program Operation Timings..........................................
Figure 16. Accelerated Program Timing Diagram..........................
Figure 17. Chip/Sector Erase Operation Timings ..........................
Figure 18. Data# Polling Timings
(During Embedded Algorithms)......................................................
Figure 19. Toggle Bit Timings
(During Embedded Algorithms)......................................................
Figure 20. DQ2 vs. DQ6.................................................................
40
40
41
42
43
43
Hardware Data Protection ...................................................... 20
Low V
CC
Write Inhibit .......................................................................20
Write Pulse “Glitch” Protection ........................................................21
Logical Inhibit ..................................................................................21
Power-Up Write Inhibit ....................................................................21
Common Flash Memory Interface (CFI) . . . . . . . 21
Table 6. CFI Query Identification String ..........................................
Table 7. System Interface String.....................................................
Table 8. Device Geometry Definition ..............................................
Table 9. Primary Vendor-Specific Extended Query ........................
21
22
22
23
Temporary Sector Unprotect .................................................. 44
Figure 21. Temporary Sector Group Unprotect Timing Diagram ... 44
Figure 22. Sector Group Protect and Unprotect Timing Diagram .. 45
Command Definitions . . . . . . . . . . . . . . . . . . . . . 23
Reading Array Data ................................................................ 23
Reset Command ..................................................................... 24
Autoselect Command Sequence ............................................ 24
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 24
Word Program Command Sequence ..................................... 24
Unlock Bypass Command Sequence ..............................................25
Figure 3. Program Operation .......................................................... 25
Alternate CE# Controlled Erase and Program Operations ..... 46
Figure 23. Alternate CE# Controlled Write
(Erase/Program) Operation Timings .............................................. 47
Chip Erase Command Sequence ........................................... 25
Sector Erase Command Sequence ........................................ 26
Erase Suspend/Erase Resume Commands ........................... 26
Program Suspend/Program Resume Commands .................. 27
Figure 4. Erase Operation............................................................... 27
Command Definitions ............................................................. 28
Table 10. Command Definitions...................................................... 28
Erase And Programming Performance . . . . . . . 48
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 48
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 48
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 49
FBE063—63-Ball Fine-Pitch Ball Grid Array
(FBGA) 11 x 12 mm package ................................................. 49
LAA064—64-Ball Fortified Ball Grid Array (Fortified
BGA) 13 x 11 mm package ..................................................... 50
TS 048—48-Pin Standard TSOP ............................................ 51
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 52
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 29
August 28, 2002
Am29LV641GH/L / Am29LV640GU
3
A D V A N C E
I N F O R M A T I O N
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Option
Max Access Time (ns)
CE# Access (ns)
OE# Access (ns)
Note:
See “AC Characteristics” for full specifications.
Standard Voltage Range: V
CC
= 2.7–3.6 V
Am29LV641GH/L / Am29LV640GU
70
70
70
35
90
90
90
35
100
100
100
50
BLOCK DIAGRAM
DQ15
–
DQ0
V
CC
V
SS
RESET#
Erase Voltage
Generator
V
IO
Input/Output
Buffers
Sector Switches
WE#
WP#
ACC
RY/BY#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data
Latch
CE#
OE#
STB
V
CC
Detector
Timer
Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A21–A0
4
Am29LV641GH/L / Am29LV640GU
August 28, 2002
A D V A N C E
I N F O R M A T I O N
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE#
RESET#
ACC
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-Pin Standard TSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
V
IO
V
SS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
A16
V
IO
V
SS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-Pin Reverse TSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE#
RESET#
ACC
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
August 28, 2002
Am29LV641GH/L / Am29LV640GU
5
Microcontroller MCU
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