S71NS128NA0/S71NS064NA0 Based MCPs
Stacked Multi-Chip Product (MCP) MirrorBit™ Flash Memory
and pSRAM 128 Mb (8M x 16-bit) and 64 Mb (4M x 16-Bit),
110 nm CMOS 1.8 Volt-only, Multiplexed, Simultaneous Read/
Write, Burst Mode Flash Memory with
16 Mb (1M x 16-Bit) pSRAM
Data Sheet
ADVANCE
INFORMATION
1RWLFH WR 5HDGHUV
7KLV GRFXPHQW VWDWHV WKH FXUUHQW WHFKQLFDO VSHFLILFDWLRQV
UHJDUGLQJ WKH 6SDQVLRQ SURGXFW V
GHVFULEHG KHUHLQ (DFK SURGXFW GHVFULEHG
KHUHLQ PD\ EH GHVLJQDWHG DV $GYDQFH ,QIRUPDWLRQ 3UHOLPLQDU\ RU )XOO
3URGXFWLRQ 6HH
1RWLFH 2Q 'DWD 6KHHW 'HVLJQDWLRQV
IRU GHILQLWLRQV
Publication Number
S71NS128_064NA0_00
Revision
A
Amendment
1
Issue Date
September 23, 2005
7KLV GRFXPHQW FRQWDLQV LQIRUPDWLRQ RQ D SURGXFW XQGHU GHYHORSPHQW DW 6SDQVLRQ //& 7KH LQIRUPDWLRQ LV LQWHQGHG WR KHOS \RX HYDOXDWH WKLV SURGXFW 'R QRW GHVLJQ LQ
WKLV SURGXFW ZLWKRXW FRQWDFWLQJ WKH IDFWRU\ 6SDQVLRQ UHVHUYHV WKH ULJKW WR FKDQJH RU GLVFRQWLQXH ZRUN RQ WKLV SURSRVHG SURGXFW ZLWKRXW QRWLFH
A d v a n c e
I n f o r m a t i o n
Notice On Data Sheet Designations
6SDQVLRQ //& LVVXHV GDWD VKHHWV ZLWK $GYDQFH ,QIRUPDWLRQ RU 3UHOLPLQDU\ GHVLJQDWLRQV WR DGYLVH
UHDGHUV RI SURGXFW LQIRUPDWLRQ RU LQWHQGHG VSHFLILFDWLRQV WKURXJKRXW WKH SURGXFW OLIH F\FOH LQ
FOXGLQJ GHYHORSPHQW TXDOLILFDWLRQ LQLWLDO SURGXFWLRQ DQG IXOO SURGXFWLRQ ,Q DOO FDVHV KRZHYHU
UHDGHUV DUH HQFRXUDJHG WR YHULI\ WKDW WKH\ KDYH WKH ODWHVW LQIRUPDWLRQ EHIRUH ILQDOL]LQJ WKHLU GH
VLJQ 7KH IROORZLQJ GHVFULSWLRQV RI 6SDQVLRQ GDWD VKHHW GHVLJQDWLRQV DUH SUHVHQWHG KHUH WR
KLJKOLJKW WKHLU SUHVHQFH DQG GHILQLWLRQV
$GYDQFH ,QIRUPDWLRQ
7KH $GYDQFH ,QIRUPDWLRQ GHVLJQDWLRQ LQGLFDWHV WKDW 6SDQVLRQ //& LV GHYHORSLQJ RQH RU PRUH VSH
FLILF SURGXFWV EXW KDV QRW FRPPLWWHG DQ\ GHVLJQ WR SURGXFWLRQ ,QIRUPDWLRQ SUHVHQWHG LQ D
GRFXPHQW ZLWK WKLV GHVLJQDWLRQ LV OLNHO\ WR FKDQJH DQG LQ VRPH FDVHV GHYHORSPHQW RQ WKH SURG
XFW PD\ GLVFRQWLQXH 6SDQVLRQ //& WKHUHIRUH SODFHV WKH IROORZLQJ FRQGLWLRQV XSRQ $GYDQFH
,QIRUPDWLRQ FRQWHQW
³7KLV GRFXPHQW FRQWDLQV LQIRUPDWLRQ RQ RQH RU PRUH SURGXFWV XQGHU GHYHORSPHQW DW 6SDQVLRQ //& 7KH
LQIRUPDWLRQ LV LQWHQGHG WR KHOS \RX HYDOXDWH WKLV SURGXFW 'R QRW GHVLJQ LQ WKLV SURGXFW ZLWKRXW FRQ
WDFWLQJ WKH IDFWRU\ 6SDQVLRQ //& UHVHUYHV WKH ULJKW WR FKDQJH RU GLVFRQWLQXH ZRUN RQ WKLV SURSRVHG
SURGXFW ZLWKRXW QRWLFH´
3UHOLPLQDU\
7KH 3UHOLPLQDU\ GHVLJQDWLRQ LQGLFDWHV WKDW WKH SURGXFW GHYHORSPHQW KDV SURJUHVVHG VXFK WKDW D
FRPPLWPHQW WR SURGXFWLRQ KDV WDNHQ SODFH 7KLV GHVLJQDWLRQ FRYHUV VHYHUDO DVSHFWV RI WKH SURG
XFW OLIH F\FOH LQFOXGLQJ SURGXFW TXDOLILFDWLRQ LQLWLDO SURGXFWLRQ DQG WKH VXEVHTXHQW SKDVHV LQ WKH
PDQXIDFWXULQJ SURFHVV WKDW RFFXU EHIRUH IXOO SURGXFWLRQ LV DFKLHYHG &KDQJHV WR WKH WHFKQLFDO
VSHFLILFDWLRQV SUHVHQWHG LQ D 3UHOLPLQDU\ GRFXPHQW VKRXOG EH H[SHFWHG ZKLOH NHHSLQJ WKHVH DV
SHFWV RI SURGXFWLRQ XQGHU FRQVLGHUDWLRQ 6SDQVLRQ SODFHV WKH IROORZLQJ FRQGLWLRQV XSRQ
3UHOLPLQDU\ FRQWHQW
³7KLV GRFXPHQW VWDWHV WKH FXUUHQW WHFKQLFDO VSHFLILFDWLRQV UHJDUGLQJ WKH 6SDQVLRQ SURGXFW V
GHVFULEHG
KHUHLQ 7KH 3UHOLPLQDU\ VWDWXV RI WKLV GRFXPHQW LQGLFDWHV WKDW SURGXFW TXDOLILFDWLRQ KDV EHHQ FRPSOHWHG
DQG WKDW LQLWLDO SURGXFWLRQ KDV EHJXQ 'XH WR WKH SKDVHV RI WKH PDQXIDFWXULQJ SURFHVV WKDW UHTXLUH
PDLQWDLQLQJ HIILFLHQF\ DQG TXDOLW\ WKLV GRFXPHQW PD\ EH UHYLVHG E\ VXEVHTXHQW YHUVLRQV RU PRGLILFD
WLRQV GXH WR FKDQJHV LQ WHFKQLFDO VSHFLILFDWLRQV´
&RPELQDWLRQ
6RPH GDWD VKHHWV ZLOO FRQWDLQ D FRPELQDWLRQ RI SURGXFWV ZLWK GLIIHUHQW GHVLJQDWLRQV $GYDQFH
,QIRUPDWLRQ 3UHOLPLQDU\ RU )XOO 3URGXFWLRQ
7KLV W\SH RI GRFXPHQW ZLOO GLVWLQJXLVK WKHVH SURG
XFWV DQG WKHLU GHVLJQDWLRQV ZKHUHYHU QHFHVVDU\ W\SLFDOO\ RQ WKH ILUVW SDJH WKH RUGHULQJ
LQIRUPDWLRQ SDJH DQG SDJHV ZLWK WKH '& &KDUDFWHULVWLFV WDEOH DQG WKH $& (UDVH DQG 3URJUDP
WDEOH LQ WKH WDEOH QRWHV
7KH GLVFODLPHU RQ WKH ILUVW SDJH UHIHUV WKH UHDGHU WR WKH QRWLFH RQ WKLV
SDJH
)XOO 3URGXFWLRQ 1R 'HVLJQDWLRQ RQ 'RFXPHQW
:KHQ D SURGXFW KDV EHHQ LQ SURGXFWLRQ IRU D SHULRG RI WLPH VXFK WKDW QR FKDQJHV RU RQO\ QRPLQDO
FKDQJHV DUH H[SHFWHG WKH 3UHOLPLQDU\ GHVLJQDWLRQ LV UHPRYHG IURP WKH GDWD VKHHW 1RPLQDO
FKDQJHV PD\ LQFOXGH WKRVH DIIHFWLQJ WKH QXPEHU RI RUGHULQJ SDUW QXPEHUV DYDLODEOH VXFK DV WKH
DGGLWLRQ RU GHOHWLRQ RI D VSHHG RSWLRQ WHPSHUDWXUH UDQJH SDFNDJH W\SH RU 9
,2
UDQJH &KDQJHV
PD\ DOVR LQFOXGH WKRVH QHHGHG WR FODULI\ D GHVFULSWLRQ RU WR FRUUHFW D W\SRJUDSKLFDO HUURU RU LQ
FRUUHFW VSHFLILFDWLRQ 6SDQVLRQ //& DSSOLHV WKH IROORZLQJ FRQGLWLRQV WR GRFXPHQWV LQ WKLV
FDWHJRU\
³7KLV GRFXPHQW VWDWHV WKH FXUUHQW WHFKQLFDO VSHFLILFDWLRQV UHJDUGLQJ WKH 6SDQVLRQ SURGXFW V
GHVFULEHG
KHUHLQ 6SDQVLRQ //& GHHPV WKH SURGXFWV WR KDYH EHHQ LQ VXIILFLHQW SURGXFWLRQ YROXPH VXFK WKDW VXE
VHTXHQW YHUVLRQV RI WKLV GRFXPHQW DUH QRW H[SHFWHG WR FKDQJH +RZHYHU W\SRJUDSKLFDO RU VSHFLILFDWLRQ
FRUUHFWLRQV RU PRGLILFDWLRQV WR WKH YDOLG FRPELQDWLRQV RIIHUHG PD\ RFFXU´
4XHVWLRQV UHJDUGLQJ WKHVH GRFXPHQW GHVLJQDWLRQV PD\ EH GLUHFWHG WR \RXU ORFDO $0' RU )XMLWVX
VDOHV RIILFH
ii
S71NS128NA0/S71NS064NA0 Based MCPs
S71NS128_064NA0_00_A1 September 23, 2005
S71NS128NA0/S71NS064NA0 Based MCPs
Stacked Multi-Chip Product (MCP) MirrorBit™ Flash Memory
and pSRAM 128 Mb (8M x 16-bit) and 64 Mb (4M x 16-Bit),
110 nm CMOS 1.8 Volt-only, Multiplexed, Simultaneous Read/
Write, Burst Mode Flash Memory with 16 Mb (1M x 16-Bit)
pSRAM
Data Sheet
ADVANCE
INFORMATION
Distinctive Characteristics
0&3 )HDWXUHV
3RZHU VXSSO\ YROWDJH RI 9 WR 9
6SHHG
²
²
)ODVK
0+] 0+] 0+]
$V\QFKURQRXV DFFHVV WLPH
)ODVK
BQV S65$0
BQV
[ [ PP EDOO )%*$ 6161$
±& WR &
3DFNDJHV
²
²
2SHUDWLQJ 7HPSHUDWXUH
²
General Description
7KH 616 6HULHV LV D SURGXFW OLQH RI VWDFNHG 0XOWL&KLS 3URGXFW 0&3
SDFNDJHV
DQG FRQVLVWV RI
2QH PXOWLSOH[HG )/$6+ PHPRU\ GLH 161 RU 161
2QH S65$0
7KH SURGXFWV FRYHUHG E\ WKLV GRFXPHQW DUH OLVWHG LQ WKH WDEOH EHORZ )RU GHWDLOV DERXW WKHLU VSHF
LILFDWLRQV SOHDVH UHIHU WR WKH LQGLYLGXDO GDWD VKHHWV LQFOXGHG LQ WKLV GRFXPHQW
IRU IXUWKHU
GHWDLOV
)ODVK 'HQVLW\
'HYLFH
6161$
6161$
0E
0E
365$0 'HQVLW\
0E
0E
Publication Number
S71NS128_064NA0_00
Revision
A
Amendment
1
Issue Date
September 23, 2005
7KLV GRFXPHQW FRQWDLQV LQIRUPDWLRQ RQ D SURGXFW XQGHU GHYHORSPHQW DW 6SDQVLRQ //& 7KH LQIRUPDWLRQ LV LQWHQGHG WR KHOS \RX HYDOXDWH WKLV SURGXFW 'R QRW GHVLJQ LQ
WKLV SURGXFW ZLWKRXW FRQWDFWLQJ WKH IDFWRU\ 6SDQVLRQ UHVHUYHV WKH ULJKW WR FKDQJH RU GLVFRQWLQXH ZRUN RQ WKLV SURSRVHG SURGXFW ZLWKRXW QRWLFH
A d v a n c e
I n f o r m a t i o n
Contents
S71NS128NA0/S71NS064NA0 Based MCPs . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
MCP Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
S71NS128NA0, 44-ball Very-Thin FBGA (NLB044) Pinout, NS128N + 16 PSRAM................................................................9
S71NS064NA0, 44-ball Very-Thin FBGA (NLD044) Pinout, NS064N + 16 PSRAM .......................................................... 10
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Order Number .........................................................................................................................................................................................12
Physical Dimension — S71NS128NA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
NLB044, 44-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 9.2 x 8 mm Package .......................................................13
Physical Dimension — S71NS064NA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
NLD044, 44-Ball Very Thin Fine-pitch Ball Grid Array (BGA) 7.7 x 6.2 mm....................................................................... 14
S29NSxxxN MirrorBit
TM
Flash Family . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Block Diagram of Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
VersatileIO™ (V
IO
) Control.................................................................................................................................................................24
Requirements for Asynchronous Read Operation (Non-Burst)..............................................................................................24
Requirements for Synchronous (Burst) Read Operation...........................................................................................................25
Continuous Burst .........................................................................................................................................................................25
8-, 16-, and 32-Word Linear Burst with Wrap Around ....................................................................................................27
8-, 16-, and 32-Word Linear Burst without Wrap Around .............................................................................................27
Programmable Wait State................................................................................................................................................................... 28
Configuration Register ......................................................................................................................................................................... 28
Handshaking Feature............................................................................................................................................................................. 28
Simultaneous Read/Write Operations with Zero Latency ....................................................................................................... 28
Writing Commands/Command Sequences.................................................................................................................................... 28
Accelerated Program and Erase Operations................................................................................................................................. 28
Write Buffer Programming Operation............................................................................................................................................ 29
Autoselect Mode.....................................................................................................................................................................................30
Advanced Sector Protection and Unprotection............................................................................................................................30
Sector Protection.....................................................................................................................................................................................31
Persistent Sector Protection ................................................................................................................................................................31
Persistent Protection Bit (PPB) ................................................................................................................................................32
Persistent Protection Bit Lock (PPB Lock Bit) in Persistent Sector Protection Mode ..........................................32
Dynamic Protection Bit (DYB) ................................................................................................................................................32
Persistent Sector Protection Mode Lock Bit..................................................................................................................................33
Password Sector Protection................................................................................................................................................................34
64-bit Password .......................................................................................................................................................................................34
Password Mode Lock Bit......................................................................................................................................................................34
Persistent Protection Bit Lock (PPB Lock Bit) in Password Sector Protection Mode......................................................35
Hardware Data Protection Mode......................................................................................................................................................35
Write Protect (WP#) .................................................................................................................................................................35
WP# Boot Sector Protection .............................................................................................................................................................35
Low VCC Write Inhibit ........................................................................................................................................................................36
2
S71NS128NA0/S71NS064NA0 Based MCPs
S71NS128_064NA0_00_A1 September 23, 2005
A d v a n c e
I n f o r m a t i o n
Write Pulse “Glitch” Protection ........................................................................................................................................................36
Logical Inhibit............................................................................................................................................................................................36
Power-Up Write Inhibit .............................................................................................................................................................36
Lock Register............................................................................................................................................................................................36
Standby Mode .........................................................................................................................................................................................37
Automatic Sleep Mode ..........................................................................................................................................................................37
RESET#: Hardware Reset Input .........................................................................................................................................................37
V
CC
Power-up and Power-down Sequencing .....................................................................................................................37
Output Disable Mode............................................................................................................................................................................37
SecSi™ (Secured Silicon) Sector Flash Memory Region...............................................................................................................37
Factory Locked: Factor SecSi Sector Programmed and Protected At the Factory .................................................38
Customer SecSi Sector ...............................................................................................................................................................38
Common Flash Memory Interface (CFI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Reading Array Data.................................................................................................................................................................................51
Set Configuration Register Command Sequence...........................................................................................................................51
Read Configuration Register Command Sequence .......................................................................................................................51
Read Mode Setting .......................................................................................................................................................................52
Programmable Wait State Configuration .............................................................................................................................52
Programmable Wait State .........................................................................................................................................................52
Handshaking ...................................................................................................................................................................................53
Burst Length Configuration .......................................................................................................................................................53
Burst Wrap Around ....................................................................................................................................................................53
RDY Configuration ......................................................................................................................................................................53
RDY Polarity ..................................................................................................................................................................................54
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Reset Command......................................................................................................................................................................................55
Autoselect Command Sequence .......................................................................................................................................................57
Enter SecSi™ Sector/Exit SecSi Sector Command Sequence.....................................................................................................57
Unlock Bypass Command Sequence ..................................................................................................................................... 58
Program Command Sequence ........................................................................................................................................................... 58
Program Command Sequence ................................................................................................................................................. 58
Program Command Sequence (Unlock Bypass Mode) .................................................................................................... 58
Accelerated Program............................................................................................................................................................................ 58
Write Buffer Programming Command Sequence .........................................................................................................................59
Chip Erase Command Sequence .........................................................................................................................................................61
Chip Erase Command Sequence ..............................................................................................................................................61
Sector Erase Command Sequence.....................................................................................................................................................62
Sector Erase Command Sequence ..........................................................................................................................................62
Accelerated Sector Erase ..........................................................................................................................................................63
Erase Suspend/Erase Resume Commands...................................................................................................................................... 64
Program Suspend/Program Resume Commands ......................................................................................................................... 64
Lock Register Command Set Definitions ........................................................................................................................................65
Password Protection Command Set Definitions ..........................................................................................................................65
Non-Volatile Sector Protection Command Set Definitions ..................................................................................................... 66
Global Volatile Sector Protection Freeze Command Set.......................................................................................................... 68
Volatile Sector Protection Command Set...................................................................................................................................... 68
Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
DQ7: Data# Polling ................................................................................................................................................................................74
RDY: Ready .............................................................................................................................................................................................76
DQ6: Toggle Bit I....................................................................................................................................................................................76
DQ2: Toggle Bit II...................................................................................................................................................................................76
Reading Toggle Bits DQ6/DQ2 ......................................................................................................................................................... 78
DQ5: Exceeded Timing Limits ........................................................................................................................................................... 78
DQ3: Sector Erase Start Timeout State Indicator........................................................................................................................79
September 23, 2005 S71NS128_064NA0_00_A1
S71NS128NA0/S71NS064NA0 Based MCPs
3
京公网安备 11010802033920号
EEWORLD
