ST24C01M3013TR datasheet, PDF - EEWORLD Datasheet

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ST24C01M3013TR: Description128X8 I2C/2-WIRE SERIAL EEPROM, PDSO8, PLASTIC, SO-8; Categorystorage storage; File Size143KB，16 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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ST24C01M3013TR Overview

128X8 I2C/2-WIRE SERIAL EEPROM, PDSO8, PLASTIC, SO-8

ST24C01M3013TR Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	STMicroelectronics
Parts packaging code	SOIC
package instruction	SOP, SOP8,.25
Contacts	8
Reach Compliance Code	not_compliant
ECCN code	EAR99
Other features	1000K ERASE/WRITE CYCLES MIN.; DATA RETENTION > 10 YEARS
Maximum clock frequency (fCLK)	0.1 MHz
Data retention time - minimum	40
Durability	1000000 Write/Erase Cycles
I2C control byte	1010DDDR
JESD-30 code	R-PDSO-G8
JESD-609 code	e0
length	4.9 mm
memory density	1024 bit
Memory IC Type	EEPROM
memory width	8
Number of functions	1
Number of terminals	8
word count	128 words
character code	128
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
organize	128X8
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3/5 V
Certification status	Not Qualified
Maximum seat height	1.75 mm
Serial bus type	I2C
Maximum slew rate	0.002 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.9 mm
Maximum write cycle time (tWC)	10 ms

ST24C01M3013TR Preview

ST24/25C01, ST24C01R

ST24/25W01

SERIAL 1K (128 x 8) EEPROM

NOT FOR NEW DESIGN

1 MILLION ERASE/WRITE CYCLES with

40 YEARS DATA RETENTION

SINGLE SUPPLY VOLTAGE:

– 3V to 5.5V for ST24x01 versions

– 2.5V to 5.5V for ST25x01 versions

– 1.8V to 5.5V for ST24C01R version only

HARDWARE WRITE CONTROL VERSIONS:

ST24W01 and ST25W01

TWO WIRE SERIAL INTERFACE, FULLY I

BUS COMPATIBLE

BYTE and MULTIBYTE WRITE (up to 4

BYTES)

PAGE WRITE (up to 8 BYTES)

BYTE, RANDOM and SEQUENTIAL READ

MODES

SELF TIMED PROGRAMMING CYCLE

AUTOMATIC ADDRESS INCREMENTING

ENHANCED ESD/LATCH UP

PERFORMANCES

ST24C/W01 are replaced by the M24C01

ST25C/W01 are replaced by the M24C01-W

ST24C01R is replaced by the M24C01-R

DESCRIPTION

This specification covers a range of 1K bits I

C bus

EEPROM products, t he ST24/25C01, the

ST24C01R and the ST24/25W01. In the text, prod-

ucts are referred to as ST24/25x01, where "x" is:

"C" for Standard version and "W" for hardware

Write Control version.

Table 1. Signal Names

E0-E2

SDA

SCL

MODE

Chip Enable Inputs

Serial Data Address Input/Output

Serial Clock

Multibyte/Page Write Mode

(C version)

Write Control (W version)

Supply Voltage

Ground

PSDIP8 (B)

0.25mm Frame

SO8 (M)

150mil Width

Figure 1. Logic Diagram

VCC

E0-E2

SCL

MODE/WC*

ST24x01

ST25x01

ST24C01R

SDA

VSS

AI00839D

Note:

WC signal is only available for ST24/25W01 products.

November 1997

This is information on a product still in production but not recommended for new design

1/16

ST24/25C01, ST24C01R, ST24/25W01

Figure 2A. DIP Pin Connections

Figure 2B. SO Pin Connections

ST24x01

ST25x01

ST24C01R

VSS

AI00840D

ST24x01

ST25x01

ST24C01R

VCC

MODE/WC

SCL

SDA

VSS

AI00841E

VCC

MODE/WC

SCL

SDA

Table 2. Absolute Maximum Ratings

(1)

Symbol

STG

LEAD

ESD

Parameter

Ambient Operating Temperature

Storage Temperature

Lead Temperature, Soldering

Input or Output Voltages

Supply Voltage

Electrostatic Discharge Voltage (Human Body model)

(2)

Electrostatic Discharge Voltage (Machine model)

(3)

(SO8 package)

(PSDIP8 package)

40 sec

10 sec

Value

–40 to 125

–65 to 150

215

260

–0.6 to 6.5

–0.3 to 6.5

4000

500

Unit

°C

Notes:

1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other

relevant quality documents.

2. MIL-STD-883C, 3015.7 (100pF, 1500

Ω).

3. EIAJ IC-121 (Condition C) (200pF, 0

Ω).

DESCRIPTION

(cont’d)

The ST24/25x01 are 1K bit electrically erasable

programmable memories (EEPROM), organized

as 128 x 8 bits. They are manufactured in SGS-

THOMSON’s Hi-Endurance Advanced CMOS

technology which guarantees an endurance of one

million erase/write cycles with a data retention of

40 years. The memories operate with a power

supply value as low as 1.8V for the ST24C01R only.

Both Plastic Dual-in-Line and Plastic Small Outline

packages are available.

The memories are compatible with the I

C stand-

ard, two wire serial interface which uses a bi-direc-

tional data bus and serial clock. The memories

carry a built-in 4 bit, unique device identification

code (1010) corresponding to the I

C bus defini-

tion. This is used together with 3 chip enable inputs

(E2, E1, E0) so that up to 8 x 1K devices may be

attached to the I

C bus and selected individually.

The memories behave as a slave device in the I

protocol with all memory operations synchronized

by the serial clock. Read and write operations are

initiated by a START condition generated by the

bus master. The START condition is followed by a

stream of 7 bits (identification code 1010), plus one

read/write bit and terminated by an acknowledge

bit.

2/16

ST24/25C01, ST24C01R, ST24/25W01

Table 3. Device Select Code

Device Code

Bit

Device Select

Note:

The MSB b7 is sent first.

Chip Enable

Table 4. Operating Modes

(1)

Mode

Current Address Read

Random Address Read

Sequential Read

Byte Write

Multibyte Write

(2)

Page Write

RW bit

’1’

’0’

’1’

’0’

1 to 128

MODE

Bytes

Initial Sequence

START, Device Select, RW = ’1’

START, Device Select, RW = ’0’, Address,

reSTART, Device Select, RW = ’1’

Similar to Current or Random Mode

START, Device Select, RW = ’0’

Notes:

1. X = V

or V

2. Multibyte Write not available in ST24/25W01 versions.

When writing data to the memory it responds to the

8 bits received by asserting an acknowledge bit

during the 9th bit time. When data is read by the

bus master, it acknowledges the receipt of the data

bytes in the same way. Data transfers are termi-

nated with a STOP condition.

Power On Reset: V

lock out write protect.

order to prevent data corruption and inadvertent

write operations during power up, a Power On

Reset (POR) circuit is implemented. Until the V

voltage has reached the POR threshold value, the

internal reset is active, all operations are disabled

and the device will not respond to any command.

In the same way, when V

drops down from the

operating voltage to below the POR threshold

value, all operations are disabled and the device

will not respond to any command. A stable V

must be applied before applying any logic signal.

SIGNAL DESCRIPTIONS

Serial Clock (SCL).

The SCL input pin is used to

synchronize all data in and out of the memory. A

resistor can be connected from the SCL line to V

to act as a pull up (see Figure 3).

Serial Data (SDA).

The SDA pin is bi-directional

and is used to transfer data in or out of the memory.

It is an open drain output that may be wire-OR’ed

with other open drain or open collector signals on

the bus. A resistor must be connected from the SDA

bus line to V

to act as pull up (see Figure 3).

Chip Enable (E0 - E2).

These chip enable inputs

are used to set the 3 least significant bits (b3, b2,

b1) of the 7 bit device select code. These inputs

may be driven dynamically or tied to V

or V

establish the device select code.

Mode (MODE).

The MODE input is available on pin

7 (see also WC feature) and may be driven dynami-

cally. It must be at V

or V

for the Byte Write

mode, V

for Multibyte Write mode or V

for Page

Write mode. When unconnected, the MODE input

is internally read as V

(Multibyte Write mode).

Write Control (WC).

An hardware Write Control

feature (WC) is offered only for ST24W01 and

ST25W01 versions on pin 7. This feature is usefull

to protect the contents of the memory from any

erroneous erase/write cycle. The Write Control sig-

nal is used to enable (WC = V

) or disable (WC =

) the internal write protection. When uncon-

nected, the WC input is internally read as V

and

the memory area is not write protected.

3/16

ST24/25C01, ST24C01R, ST24/25W01

SIGNAL DESCRIPTION

(cont’d)

The devices with this Write Control feature no

longer support the Multibyte Write mode of opera-

tion, however all other write modes are fully sup-

ported.

Refer to the AN404 Application Note for more de-

tailed information about Write Control feature.

DEVICE OPERATION

C Bus Background

The ST24/25x01 support the I

C protocol. This

protocol defines any device that sends data onto

the bus as a transmitter and any device that reads

the data as a receiver. The device that controls the

data transfer is known as the master and the other

as the slave. The master will always initiate a data

transfer and will provide the serial clock for syn-

chronisation. The ST24/25x01 are always slave

devices in all communications.

Start Condition.

START is identified by a high to

low transition of the SDA line while the clock SCL

is stable in the high state. A START condition must

precede any command for data transfer. Except

during a programming cycle, the ST24/25x01 con-

tinuously monitor the SDA and SCL signals for a

START condition and will not respond unless one

is given.

Stop Condition.

STOP is identified by a low to high

transition of the SDA line while the clock SCL is

stable in the high state. A STOP condition termi-

nates communication between the ST24/25x01

and the bus master. A STOP condition at the end

of a Read command, after and only after a No

Acknowledge, forces the standby state. A STOP

condition at the end of a Write command triggers

the internal EEPROM write cycle.

Acknowledge Bit (ACK).

An acknowledge signal

is used to indicate a successfull data transfer. The

bus transmitter, either master or slave, will release

the SDA bus after sending 8 bits of data. During the

9th clock pulse period the receiver pulls the SDA

bus low to acknowledge the receipt of the 8 bits of

data.

Data Input.

During data input the ST24/25x01

sample the SDA bus signal on the rising edge of

the clock SCL. Note that for correct device opera-

tion the SDA signal must be stable during the clock

low to high transition and the data must change

ONLY when the SCL line is low.

Memory Addressing.

To start communication be-

tween the bus master and the slave ST24/25x01,

the master must initiate a START condition. Follow-

ing this, the master sends onto the SDA bus line 8

bits (MSB first) corresponding to the device select

code (7 bits) and a READ or WRITE bit.

Figure 3. Maximum R

Value versus Bus Capacitance (C

BUS

) for an I

C Bus

VCC

RL max (kΩ)

MASTER

SDA

SCL

CBUS

VCC = 5V

100

200

CBUS (pF)

300

400

AI01100

4/16

ST24/25C01, ST24C01R, ST24/25W01

Table 5. Input Parameters

(1)

= 25

°C,

f = 100 kHz )

Symbol

WCL

WCH

Parameter

Input Capacitance (SDA)

Input Capacitance (other pins)

WC Input Impedance (ST24/25W01)

Low-pass filter input time constant

(SDA and SCL)

≤

0.3 V

≥

0.7 V

500

100

Test Condition

Min

Max

Unit

kΩ

Note:

1. Sampled only, not 100% tested.

Table 6. DC Characteristics

= 0 to 70°C, –20 to 85°C or –40 to 85°C; V

= 3V to 5.5V, 2.5V to 5.5V or 1.8V to 5.5V)

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Supply Current (ST24 series)

Supply Current (ST25 series)

Supply Current (Standby)

(ST24 series)

Test Condition

≤

OUT

≤

SDA in Hi-Z

= 5V, f

= 100kHz

(Rise/Fall time < 10ns)

= 2.5V, f

= 100kHz

= V

or V

= 5V

= V

or V

= 5V, f

= 100kHz

= V

or V

= 2.5V

= V

or V

= 2.5V, f

= 100kHz

= V

or V

= 3.6V

= V

or V

= 3.6V, f

= 100kHz

= V

or V

= 1.8V

= V

or V

= 1.8V, f

= 100kHz

–0.3

0.7 V

–0.3

– 0.5

= 3mA, V

= 5V

= 2.1mA, V

= 2.5V

= 1mA, V

= 1.8V

Min

Max

±2

100

300

0.3 V

+ 1

0.5

+ 1

0.4

0.3

Unit

µA

CC1

CC2

Supply Current (Standby)

(ST25 series)

CC3

Supply Current (Standby)

(ST24C01R)

CC4

Supply Current (Standby)

(ST24C01R)

Input Low Voltage (SCL, SDA)

Input High Voltage (SCL, SDA)

Input Low Voltage

(E0-E2, MODE, WC)

Input High Voltage

(E0-E2, MODE, WC)

Output Low Voltage (ST24 series)

Output Low Voltage (ST25 series)

Output Low Voltage

(ST24C01R)

5/16

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