D750AUT1B datasheet, PDF - EEWORLD Datasheet

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D750AUT1B: DescriptionMicroprocessor, 32-Bit, 750MHz, CMOS, CPGA453, STAGGERED, CERAMIC, PGA-453; CategoryThe embedded processor and controller Microcontrollers and processors; File Size586KB，88 Pages; ManufacturerAMD; Websitehttp://www.amd.com

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D750AUT1B Overview

Microprocessor, 32-Bit, 750MHz, CMOS, CPGA453, STAGGERED, CERAMIC, PGA-453

D750AUT1B Parametric

Parameter Name	Attribute value
Maker	AMD
Parts packaging code	PGA
package instruction	IPGA, SPGA462,37X37
Contacts	453
Reach Compliance Code	compliant
ECCN code	3A991.A.2
Other features	TEMPERATURE OF PROCESSOR DIE 90 DEG CELCIUS
Address bus width	15
bit size	32
boundary scan	YES
maximum clock frequency	100 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CPGA-P453
length	49.53 mm
low power mode	YES
Number of terminals	453
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	IPGA
Encapsulate equivalent code	SPGA462,37X37
Package shape	SQUARE
Package form	GRID ARRAY, INTERSTITIAL PITCH
power supply	1.6,2.5 V
Certification status	Not Qualified
Maximum seat height	3.422 mm
speed	750 MHz
Maximum slew rate	20900 mA
Maximum supply voltage	1.7 V
Minimum supply voltage	1.5 V
Nominal supply voltage	1.6 V
surface mount	NO
technology	CMOS
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
width	49.53 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

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Preliminary Information

AMD Duron

Processor Model 3

Data Sheet

Publication #

23802

Rev:

Issue Date:

June 2001

Preliminary Information

23802I—June 2001

AMD Duron™ Processor Model 3 Data Sheet

Contents

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1

AMD Duron™ Processor Model 3 Microarchitecture

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Push-Pull (PP) Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

AMD Duron System Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . 6

Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1

2.2

2.3

2.4

Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1

Power Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Working State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Stop Grant States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Connect and Disconnect Protocol . . . . . . . . . . . . . . . . . . . . . . 12

Connect Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2

4.3

Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CPUID Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

7.10

7.11

7.12

7.13

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Voltage Identification (VID[4:0]) . . . . . . . . . . . . . . . . . . . . . . 24

Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 24

VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . 25

Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

VCC_CORE Voltage and Current . . . . . . . . . . . . . . . . . . . . . . 27

SYSCLK and SYSCLK# AC and DC Characteristics . . . . . . 28

AMD Duron System Bus AC and DC Characteristics . . . . . . 30

General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 32

APIC Pins AC and DC Characteristics . . . . . . . . . . . . . . . . . . 34

Contents

iii

Preliminary Information

AMD Duron™ Processor Model 3 Data Sheet

23802I—June 2001

Signal and Power-Up Requirements . . . . . . . . . . . . . . . . . . . . .35

8.1

Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Sequence and Timing Description . . . . . . . . . . . . . . .

Clock Multiplier Selection (FID[3:0]). . . . . . . . . . . . . . . . . . .

Serial Initialization Packet (SIP) Protocol . . . . . . . . . . . . . . .

Processor Warm Reset Requirements . . . . . . . . . . . . . . . . . .

The AMD Duron Processor Model 3 and Northbridge

Reset Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Die Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Socket Tabs for Heatsink Clips . . . . . . . . . . . . . . . . . . . . . . .

Pin Diagram and Pin Name Abbreviations . . . . . . . . . . . . . .

Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Detailed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A20M# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AMD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AMD Duron System Bus Pins. . . . . . . . . . . . . . . . . . . . . . . . . .

Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

APIC Pins, PICCLK, PICD[1:0]# . . . . . . . . . . . . . . . . . . . . . . .

CLKFWDRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CLKIN, RSTCLK (SYSCLK) Pins . . . . . . . . . . . . . . . . . . . . . .

CONNECT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

COREFB and COREFB# Pins . . . . . . . . . . . . . . . . . . . . . . . . .

CPU_PRESENCE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DBRDY and DBREQ# Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . .

FERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FID[3:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

INIT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

INTR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

K7CLKOUT and K7CLKOUT# Pins . . . . . . . . . . . . . . . . . . . .

Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PLL Bypass and Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SADDIN[1:0]# and SADDOUT[1:0]# Pins . . . . . . . . . . . . . . .

Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SCHECK[7:0]# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2

Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

9.1

9.2

9.3

9.4

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

10.1

10.2

10.3

Contents

D750AUT1B Related Products

	D750AUT1B	D900AUT1B	D850AUT1B	D650AUT1B	D800AUT1B	D950AUT1B	D700AUT1B
Description	Microprocessor, 32-Bit, 750MHz, CMOS, CPGA453, STAGGERED, CERAMIC, PGA-453	Microprocessor, 32-Bit, 900MHz, CMOS, CPGA453, STAGGERED, CERAMIC, PGA-453	Microprocessor, 32-Bit, 850MHz, CMOS, CPGA453, STAGGERED, CERAMIC, PGA-453	Microprocessor, 32-Bit, 650MHz, CMOS, CPGA453, STAGGERED, CERAMIC, PGA-453	Microprocessor, 32-Bit, 800MHz, CMOS, CPGA453, STAGGERED, CERAMIC, PGA-453	Microprocessor, 32-Bit, 950MHz, CMOS, CPGA453, STAGGERED, CERAMIC, PGA-453	Microprocessor, 32-Bit, 700MHz, CMOS, CPGA453, STAGGERED, CERAMIC, PGA-453
Parts packaging code	PGA	PGA	PGA	PGA	PGA	PGA	PGA
package instruction	IPGA, SPGA462,37X37	IPGA, SPGA462,37X37	IPGA, SPGA462,37X37	IPGA, SPGA462,37X37	IPGA, SPGA462,37X37	IPGA, SPGA462,37X37	IPGA, SPGA462,37X37
Contacts	453	453	453	453	453	453	453
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	3A991.A.2	3A991.A.2	3A991.A.2	3A991.A.2	3A991.A.2	3A991.A.2	3A991.A.2
Address bus width	15	15	15	15	15	15	15
bit size	32	32	32	32	32	32	32
boundary scan	YES	YES	YES	YES	YES	YES	YES
maximum clock frequency	100 MHz	100 MHz	100 MHz	100 MHz	100 MHz	100 MHz	100 MHz
External data bus width	64	64	64	64	64	64	64
Format	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT
Integrated cache	YES	YES	YES	YES	YES	YES	YES
JESD-30 code	S-CPGA-P453	S-CPGA-P453	S-CPGA-P453	S-CPGA-P453	S-CPGA-P453	S-CPGA-P453	S-CPGA-P453
length	49.53 mm	49.53 mm	49.53 mm	49.53 mm	49.53 mm	49.53 mm	49.53 mm
low power mode	YES	YES	YES	YES	YES	YES	YES
Number of terminals	453	453	453	453	453	453	453
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	IPGA	IPGA	IPGA	IPGA	IPGA	IPGA	IPGA
Encapsulate equivalent code	SPGA462,37X37	SPGA462,37X37	SPGA462,37X37	SPGA462,37X37	SPGA462,37X37	SPGA462,37X37	SPGA462,37X37
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, INTERSTITIAL PITCH	GRID ARRAY, INTERSTITIAL PITCH	GRID ARRAY, INTERSTITIAL PITCH	GRID ARRAY, INTERSTITIAL PITCH	GRID ARRAY, INTERSTITIAL PITCH	GRID ARRAY, INTERSTITIAL PITCH	GRID ARRAY, INTERSTITIAL PITCH
power supply	1.6,2.5 V	1.6,2.5 V	1.6,2.5 V	1.6,2.5 V	1.6,2.5 V	1.6,2.5 V	1.6,2.5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	3.422 mm	3.422 mm	3.422 mm	3.422 mm	3.422 mm	3.422 mm	3.422 mm
speed	750 MHz	900 MHz	850 MHz	650 MHz	800 MHz	950 MHz	700 MHz
Maximum slew rate	20900 mA	24700 mA	23400 mA	18400 mA	22100 mA	25900 mA	19600 mA
Maximum supply voltage	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V	1.7 V
Minimum supply voltage	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V	1.5 V
Nominal supply voltage	1.6 V	1.6 V	1.6 V	1.6 V	1.6 V	1.6 V	1.6 V
surface mount	NO	NO	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Terminal form	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm
Terminal location	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR	PERPENDICULAR
width	49.53 mm	49.53 mm	49.53 mm	49.53 mm	49.53 mm	49.53 mm	49.53 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR
Maker	AMD	-	AMD	AMD	AMD	AMD	AMD
Other features	TEMPERATURE OF PROCESSOR DIE 90 DEG CELCIUS	-	TEMPERATURE OF PROCESSOR DIE 90 DEG CELCIUS	TEMPERATURE OF PROCESSOR DIE 90 DEG CELCIUS	TEMPERATURE OF PROCESSOR DIE 90 DEG CELCIUS	-	TEMPERATURE OF PROCESSOR DIE 90 DEG CELCIUS
Base Number Matches	-	1	1	1	1	-	-

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