HM66AEB36102/HM66AEB18202
HM66AEB9402
36-Mbit DDR II SRAM
2-word Burst
REJ03C0046-0100
Rev.1.00
Aug.28.2006
Description
The HM66AEB36102 is a 1,048,576-word by 36-bit, the HM66AEB18202 is a 2,097,152-word by 18-bit, and the
HM66AEB9402 is a 4,194,304-word by 9-bit synchronous double data rate static RAM fabricated with advanced
CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry
and a burst counter. All input registers controlled by an input clock pair (K and
K)
and are latched on the positive edge
of K and
K.
These products are suitable for applications which require synchronous operation, high speed, low voltage,
high density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1.8 V
±
0.1 V power supply for core (V
DD
)
1.4 V to V
DD
power supply for I/O (V
DDQ
)
DLL circuitry for wide output data valid window and future frequency scaling
Pipelined double data rate operation
Common data input/output bus
Two-tick burst for low DDR transaction size
Two input clocks (K and
K)
for precise DDR timing at clock rising edges only
Two output clocks (C and
C)
for precise flight time and clock skew matching-clock and data delivered together to
receiving device
Internally self-timed write control
Clock-stop capability with
µs
restart
User programmable impedance output
Fast clock cycle time: 3.0 ns (333 MHz)/3.3 ns (300 MHz)/4.0 ns (250 MHz)/5.0 ns (200 MHz)/6.0 ns (167 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
Rev.1.00 Aug 28, 2006 page 1 of 20
HM66AEB36102/18202/9402
HM66AEB18202
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
DQ9
NC
NC
NC
DQ12
NC
V
REF
NC
NC
DQ15
NC
NC
NC
TCK
3
SA
NC
NC
DQ10
DQ11
NC
DQ13
V
DDQ
NC
DQ14
NC
NC
DQ16
DQ17
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC
BW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
DQ7
NC
NC
NC
NC
V
REF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
(Top view)
HM66AEB9402
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
V
SS
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ7
NC
NC
NC
TCK
3
SA
NC
NC
NC
DQ5
NC
DQ6
V
DDQ
NC
NC
NC
NC
NC
DQ8
SA
4
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
NC
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC
BW
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
SA
NC
NC
NC
NC
NC
NC
V
REF
DQ2
NC
NC
NC
NC
NC
TMS
11
CQ
DQ4
NC
NC
DQ3
NC
NC
ZQ
NC
NC
DQ1
NC
NC
DQ0
TDI
(Top view)
Note: Note that 6C is not SA0. The
×9
product does not permit random start address on the least significant address
bit. SA0 = 0 at the start of each address.
Notes on Usage
•
Power-on initialization cycles are required for all operations, including JTAG functions, to become normal.
•
Clock recovery initialization cycles are required for read/write operations to become normal.
•
Output buffer impedance can be programmed by terminating the ZQ ball to V
SS
through a precision resistor (RQ).
The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance
matching with a tolerance of 10% is 250
Ω
typical. The total external capacitance of ZQ ball must be less than 7.5
pF.
Rev.1.00 Aug 28, 2006 page 3 of 20
HM66AEB36102/18202/9402
Pin Descriptions
Name
SA0
SA
I/O type
Input
Descriptions
Synchronous address inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. All transactions operate on a burst-of-two words (one clock period of
bus activity). SA0 is used as the lowest address bit for burst READ and burst WRITE operations
permitting a random burst start address on
×18
and
×36
devices. These inputs are ignored when
device is deselected.
Synchronous load: This input is brought low when a bus cycle sequence is to be defined. This
definition includes address and READ / WRITE direction. All transactions operate on a burst-of-
two data (one clock period of bus activity).
Synchronous read / write input: When
LD
is low, this input designates the access type (READ
when R/W is high, WRITE when R/W is low) for the loaded address. R/W must meet the setup and
hold times around the rising edge of K.
Synchronous byte writes: When low, these inputs cause their respective byte to be registered and
written during WRITE cycles. These signals must meet setup and hold times around the rising
edges of K and
K
for each of the two rising edges comprising the WRITE cycle. See Byte Write
Truth Table for signal to data relationship.
Input clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of
K. K
is ideally 180 degrees out of
phase with K. All synchronous inputs must meet setup and hold times around the clock rising
edges. These balls cannot remain V
REF
level.
Output clock: This clock pair provides a user-controlled means of tuning device output data. The
rising edge of
C
is used as the output timing reference for first output data. The rising edge of C is
used as the output timing reference for second output data. Ideally,
C
is 180 degrees out of phase
with C. C and
C
may be tied high to force the use of K and
K
as the output reference clocks
instead of having to provide C and
C
clocks. If tied high, C and
C
must remain high and not to be
toggled during device operation. These balls cannot remain V
REF
level.
DLL disable: When low, this input causes the DLL to be bypassed for stable, low frequency
operation.
Output impedance matching input: This input is used to tune the device outputs to the system data
bus impedance. DQ and CQ output impedance are set to 0.2
×
RQ, where RQ is a resistor from
this ball to ground. This ball can be connected directly to V
DDQ
, which enables the minimum
impedance mode. This ball cannot be connected directly to V
SS
or left unconnected.
IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not connected if the JTAG
function is not used in the circuit.
IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to V
SS
if the JTAG function is not
used in the circuit.
Synchronous data I/Os: Input data must meet setup and hold times around the rising edges of K
and
K.
Output data is synchronized to the respective C and
C,
or to the respective K and
K
if C
and
C
are tied high.
The
×9
device uses DQ0 to DQ8. Remaining signals are NC.
The
×18
device uses DQ0 to DQ17. Remaining signals are NC.
The
×36
device uses DQ0 to DQ35.
Synchronous echo clock outputs: The edges of these outputs are tightly matched to the
synchronous data outputs and can be used as a data valid indication. These signals run freely and
do not stop when DQ tri-states.
IEEE 1149.1 test output: 1.8 V I/O level.
Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range.
Power supply: Isolated output buffer supply. Nominally 1.5 V. 1.8 V is also permissible. See DC
Characteristics and Operating Conditions for range.
LD
Input
R/W
Input
BW
BWn
Input
K,
K
Input
C,
C
Input
DOFF
ZQ
Input
Input
TMS
TDI
TCK
DQ0 to
DQn
Input
Input
Input/
output
CQ,
CQ
Output
TDO
V
DD
V
DDQ
Output
Supply
Supply
Rev.1.00 Aug 28, 2006 page 4 of 20
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