DRAMs in FBGA packages, mounted on a 240-pin RDIMM
FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
• Parity function
OPERATING FREQUENCIES
PC2-3200
Clock Speed
CL-t
RCD
-t
RP
* Consult factory for availability
PC2-4300
266MHz
4-4-4
PC2-5300
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
200MHz
3-3-3
February 2007
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
PIN CONFIGURATION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Symbol
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
V
SS
RESET#
NC
V
SS
DQ10
DQ11
V
SS
DQ16
DQ17
V
SS
DQS2#
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DQS3#
DQS3
V
SS
DQ26
DQ27
V
SS
CB0
CB1
V
SS
DQS8#
DQS8
V
SS
CB2
CB3
V
SS
V
CCQ
CKE0
V
CC
BA2
NC
V
CCQ
A11
A7
V
CC
A5
Pin No.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Symbol
A4
V
CCQ
A2
V
CC
V
SS
V
SS
V
CC
NC
V
CC
A10/AP
BA0
V
CCQ
WE#
CAS#
V
CCQ
NC
NC
V
CCQ
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
Pin No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Symbol
V
SS
DQ4
DQ5
V
SS
DQS9
DQS9#
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DQS10
DQS10#
V
SS
NC
NC
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DQS11
DQS11#
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
DQS12
DQS12#
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DQS17
DQS17#
V
SS
CB6
CB7
V
SS
V
CCQ
NC
V
CC
NC
NC
V
CCQ
A12
A9
V
CC
A8
A6
Pin No.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Symbol
V
CCQ
A3
A1
V
CC
CK0
CK0#
V
CC
A0
V
CC
BA1
V
CCQ
RAS#
S0#
V
CCQ
ODT0
A13
V
CC
V
SS
DQ36
DQ37
V
SS
DQS13
DQS13#
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DQS14
DQS14#
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
NC
NC
V
SS
DQS15
DQS15#
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DQS16
DQS16#
V
SS
DQ62
DQ63
V
SS
V
CC
SPD
SA0
SA1
2
W3HG256M72AER-AD6
PIN NAMES
Pin Name
A0-A13
BA0 - BA2
DQ0-DQ63
CB0-CB7
DQS0-DQS17
DQS0#-DQS17#
ODT0
CK0,CK0#
CKE0
S0#
RAS#
CAS#
WE#
RESET#
SA0-SA2
SDA
SCL
V
CC,
V
CCQ
V
SS
V
REF
V
CC
SPD
NC
Function
Address Inputs
Bank Address Inputs
Data Input/Output
Check Bits
Data strobes
Data strobes complement
On-die termination control
Clock Inputs
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Register Reset Input
SPD address
SPD Data Input/Output
Serial Presence Detect(SPD) Clock Input
Core and I/O Power (1.8V)
Ground
Power Supply for Reference
SPD Power
Spare pins, No connect
February 2007
Rev. 1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
W3HG256M72AER-AD6
FUNCTIONAL BLOCK DIAGRAM
V
SS
RS0#
DQS0
DQS0#
DQ0
DQ1
DQ2
DQ3
DQS1
DQS1#
DQ8
DQ9
DQ10
DQ11
DQS2
DQS2#
DQ16
DQ17
DQ18
DQ19
DQS3
DQS3#
DQ24
DQ25
DQ26
DQ27
DQS4
DQS4#
DQ32
DQ33
DQ34
DQ35
DQS5
DQS5#
DQ40
DQ41
DQ42
DQ43
DQS6
DQS6#
DQ48
DQ49
DQ50
DQ51
DQS7
DQS7#
DQ56
DQ57
DQ58
DQ59
DQS8
DQS8#
CB0
CB1
CB2
CB3
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
CB4
CB5
CB6
CB7
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DQ60
DQ61
DQ62
DQ63
DQS17
DQS17#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DQ52
DQ53
DQ54
DQ55
DQS16
DQS16#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DQ44
DQ45
DQ46
DQ47
DQS15
DQS15#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DQ36
DQ37
DQ38
DQ39
DQS14
DQS14#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DQ28
DQ29
DQ30
DQ31
DQS13
DQS13#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DQ20
DQ21
DQ22
DQ23
DQS12
DQS12#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DQ12
DQ13
DQ14
DQ15
DQS11
DQS11#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DQ4
DQ5
DQ6
DQ7
DQS10
DQS10#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
DQS9
DQS9#
DM
I/O 0
I/O 1
I/O 2
I/O 3
CS# DQS DQS#
Serial PD
SCL
WP A0
A1
A2
SDA
SA0 SA1 SA2
V
CCSPD
V
CC
/V
CCQ
V
REF
V
SS
Serial PD
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
S0#
BA0 - BA2
A0 - A13
RAS#
CAS#
WE#
CKE0
ODT0
RESET#
PCK7
PCK7#
1:2
R
E
G
I
S
T
E
R
RST#
CK0
RS0# : DDR2 SDRAMs
RBA0 - RBA2 : DDR2 SDRAMs
RA0 - RA13 : DDR2 SDRAMs
RRAS# : DDR2 SDRAMs
RCAS# : DDR2 SDRAMs
RWE# : DDR2 SDRAMs
RCKE0 : DDR2 SDRAMs
RODT0 : DDR2 SDRAMs
PCK0-PCK6, PCK8, PCK9
CK : DDR2 SDRAMs
120Ω
CK0#
RESET#
P
L
L
OE
PCK0#-PCK6#, PCK8#, PCK9#
PCK7
CK : Register
PCK7#
CK# : Register
CK# : DDR2 SDRAMs
NOTE: All resistor values are 22 ohms unless otherwise specified.
February 2007
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
All Voltages Referenced to V
SS
Rating
Parameter
Supply Voltage
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
Symbol
V
CC
V
CCL
V
CCQ
V
REF
V
TT
Min.
1.7
1.7
1.7
0.49*V
CCQ
V
REF
-0.04
Type
1.8
1.8
1.8
0.50*V
CCQ
V
REF
W3HG256M72AER-AD6
RECOMMENDED DC OPERATING CONDITIONS
Max.
1.9
1.9
1.9
0.51*V
CCQ
V
REF
+0.04
Units
V
V
V
V
V
Notes
4
4
4
1, 2
3
There is no specific device V
CC
supply voltage requirement for SSTL-1.8 compliance. However under all conditions V
CCQ
must be less than or equal to V
CC
.
1. The value of V
REF
may be selected by the user to provide optimum noise margin in the system. Typically the value of V
REF
is expected to be about 0.5 x V
CCQ
of the transmitting
device and V
REF
is expected to track variations in V
CCQ
.
2. Peak to peak AC noise on V
REF
may not exceed ±2% V
REF
(DC).
3. V
TT
of transmitting device must track V
REF
of receiving device.
4. V
CC
, V
CCQ
and V
CC
L are tied together on this module.
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
CCQ
V
IN
, V
OUT
T
STG
Parameter
Voltage on V
CC
pin relative to V
SS
Voltage on V
CCQ
pin relative to V
SS
Voltage on any pin relative to V
SS
Storage Temperature
Rating
- 0.5 V - 2.3 V
- 0.5 V - 2.3 V
- 0.5 V - 2.3 V
-55 to +100
Units
V
V
V
°C
Notes
5
5
5
5, 6
5. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
6. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
INPUT AC LOGIC LEVEL
All voltages referenced to V
SS
Parameter
AC Input High (Logic 1) Voltage
DDR2-400 & DDR2-533
AC Input High (Logic 1) Voltage
DDR2-667
AC Input High (Logic 0) Voltage
DDR2-400 & DDR2-533
AC Input High (Logic 0) Voltage
DDR2-667
Symbol
V
IH
(AC)
V
IH
(AC)
V
IL
(AC)
V
IL
(AC)
Min
V
REF
+ 0.250
V
REF
+ 0.200
-
-
Max
-
-
V
REF
- 0.250
V
REF
- 0.200
Unit
V
V
V
V
February 2007
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
Includes DDR2 SDRAM components only
Symbol Proposed Conditions
I
CC0
W3HG256M72AER-AD6
DDR2 I
CC
SPECIFICATIONS AND CONDITIONS
806
TBD
665
1,530
534
1,260
403
1,260
Units
mA
Operating one bank active-precharge current;
t
CK
= t
CK
(I
CC
), t
RC
= t
RC
(I
CC
), t
RAS
= t
RAS
min(I
CC
); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
I
OUT
= 0mA; BL = 4, CL = CL(I
CC
), AL = 0; t
CK
= t
CK
(I
CC
), t
RC
= t
RC
(I
CC
), t
RAS
= t
RAS
min(I
CC
), t
RCD
=
t
RCD
(I
CC
); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING;
Data pattern is same as I
CC4W
Precharge power-down current;
All banks idle; t
CK
= t
CK
(I
CC
); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
Precharge quiet standby current;
All banks idle; t
CK
= t
CK
(I
CC
); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
Precharge standby current;
All banks idle; t
CK
= t
CK
(I
CC
); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
All banks open; t
CK
= t
CK
(I
CC
); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
I
CC1
TBD
1,800
1,710
1,620
mA
I
CC2P
TBD
126
126
126
mA
I
CC2Q
TBD
720
720
630
mA
I
CC2N
TBD
720
540
180
720
540
180
630
540
180
mA
mA
mA
TBD
TBD
I
CC3P
I
CC3N
Active standby current;
All banks open; t
CK
= t
CK
(I
CC
), t
RAS
= t
RAS
max(I
CC
), t
RP
= t
RP
(I
CC
); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
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