256MB, 512MB, 1GB: (x64, SR) 200-Pin DDR2 SDRAM SODIMM
Features
DDR2 SDRAM SODIMM
MT8HTF3264H(I) – 256MB
MT8HTF6464H(I) – 512MB
MT8HTF12864H(I) – 1GB
For component data sheets, refer to Micron’s Web site:
www.micron.com/products/dram/ddr2
Features
• 200-pin, small outline, dual in-line memory module
(SODIMM)
• Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, or PC2-6400
• 256MB (32 Meg x 64), 512MB (64 Meg x 64),
1GB (128 Meg x 64)
• V
DD
= V
DD
Q = +1.8V
• V
DDSPD
= +1.7V to +3.6V
• JEDEC standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• Four-bit prefetch architecture
• DLL to align DQ and DQS transitions with CK
• Multiple internal device banks for concurrent
operation
• Programmable CAS# latency (CL)
• Posted CAS# additive latency (AL)
• WRITE latency = READ latency - 1
t
CK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8,192-cycle refresh
• On-die termination (ODT)
• Serial presence detect (SPD) with EEPROM
• Gold edge contacts
• Single rank
Figure 1:
200-pin SODIMM (MO-224 R/C “B”)
Height 30mm (1.18in)
Options
•
•
•
•
Operating temperature
Commercial (0°C
≤
T
C
≤
+85°C)
Industrial (–40°C
≤
T
C
≤
+95°C)
1,2
Package
–
200-pin SODIMM (Pb-free)
• Frequency/CAS latency
3
–
2.5ns @ CL = 5 (DDR2-800)
4
–
2.5ns @ CL = 6 (DDR2-800)
4
–
3ns @ CL = 5 (DDR2-667)
–
3.75ns @ CL = 4 (DDR2-533)
–
5.0ns @ CL = 3 (DDR2-400)
• PCB Height
–
30mm (1.18in)
Marking
I
Y
-80E
-800
-667
-53E
-40E
Notes: 1.
2.
3.
4.
Table 1:
Speed
Grade
-80E
-800
-667
-53E
-40E
Industrial temperatures apply to DRAM only.
Contact Micron for product availability.
CL = CAS (READ) latency
Not available in 256MB density
Key Timing Parameters
Industry
Nomenclature
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
Data Rate (MT/s)
CL = 6
–
800
–
–
–
CL = 5
800
667
667
–
–
CL = 4
533
533
533
533
400
CL = 3
–
–
400
400
400
t
RCD
t
RP
t
RC
(ns)
12.5
15
15
15
15
(ns)
12.5
15
15
15
15
(ns)
55
55
55
55
55
PDF: 09005aef80eec96e/Source: 09005aef80eec946
HTF8C32_64_128x64HG.fm - Rev. E 6/08 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
256MB, 512MB, 1GB: (x64, SR) 200-Pin DDR2 SDRAM SODIMM
Features
Table 2:
Addressing
256MB
Refresh count
Row address
Device bank address
Device page size per bank
Device configuration
Column address
Module rank address
8K
8K A[12:0]
4 BA[1:0]
1KB
256Mb (32 Meg x 8)
1K A[9:0]
1 S0#
512MB
8K
16K A[13:0]
4 BA[1:0]
1KB
512Mb (64 Meg x 8)
1K A[9:0]
1 S0#
1GB
8K
16K A[13:0]
8 BA[2:0]
1KB
1Gb (128 Meg x 8)
1K A[9:0]
1 S0#
Table 3:
Part Numbers and Timing Parameters – 256MB Modules
Base device: MT47H32M8, 256Mb DDR2 SDRAM
Module
Density
256MB
256MB
256MB
Module
Bandwidth
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL -
t
RCD -
t
RP)
5-5-5
4-4-4
3-3-3
Part Number
1
MT8HTF3264HY-667__
MT8HTF3264HY-53E__
MT8HTF3264HY-40E__
Configuration
32 Meg x 64
32 Meg x 64
32 Meg x 64
Table 4:
Part Numbers and Timing Parameters – 512MB Modules
Base device: MT47H64M8, 512Mb DDR2 SDRAM
Module
Density
512MB
512MB
512MB
512MB
512MB
Module
Bandwidth
6.4 GB/s
6.4 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL -
t
RCD -
t
RP)
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
Part Number
1
MT8HTF6464HY-80E__
MT8HTF6464HY-800__
MT8HTF6464HY-667__
MT8HTF6464HY-53E__
MT8HTF6464HY-40E__
Configuration
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
64 Meg x 64
Table 5:
Part Numbers and Timing Parameters – 1GB Modules
Base device: MT47H128M8, 1Gb DDR2 SDRAM
Module
Density
1GB
1GB
1GB
1GB
1GB
Module
Bandwidth
6.4 GB/s
6.4 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL -
t
RCD -
t
RP)
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
Part Number
1
MT8HTF12864HY-80E__
MT8HTF12864HY-800__
MT8HTF12864HY-667__
MT8HTF12864HY-53E__
MT8HTF12864HY-40E__
Notes:
Configuration
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
1. All part numbers end with a two-place code (not shown), designating component and PCB
revisions. Consult factory for current revision codes. Example: MT8HTF6464HY-667A3.
2. For the latest componentdata sheets, see Micron’s Web site:
www.micron.com/products/dram/ddr2
PDF: 09005aef80eec96e/Source: 09005aef80eec946
HTF8C32_64_128x64HG.fm - Rev. E 6/08 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB: (x64, SR) 200-Pin DDR2 SDRAM SODIMM
Module Pin Assignments and Descriptions
Module Pin Assignments and Descriptions
Table 6:
Pin Assignments
200-Pin SODIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
V
REF
V
SS
DQ0
DQ1
V
SS
DQS0#
DQS0
V
SS
DQ2
DQ3
V
SS
DQ8
DQ9
V
SS
DQS1#
DQS1
Vss
DQ10
DQ11
V
SS
V
SS
DQ16
DQ17
V
SS
DQS2#
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
DQS2
V
SS
DQ18
DQ19
V
SS
DQ24
DQ25
V
SS
DM3
NC
V
SS
DQ26
DQ27
V
SS
CKE0
V
DD
NC
NC/BA2
V
DD
A12
A9
A8
V
DD
A5
A3
Notes:
101
A1
151
103
V
DD
153
105 A10/AP 155
107
BA0
157
109
WE#
159
161
111
V
DD
113 CAS# 163
115
NC#
165
167
117
V
DD
119
NC
169
121
V
SS
171
123 DQ32 173
125 DQ33 175
127
V
SS
177
129 DQS4# 179
131 DQS4 181
183
133
V
SS
135 DQ34 185
137 DQ35 187
139
V
SS
189
141 DQ40 191
143 DQ41 193
145
V
SS
195
147
DM5
197
199
149
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
NC
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DM7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
V
DDSPD
200-Pin SODIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
V
SS
DQ4
DQ5
V
SS
DM0
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DM1
V
SS
CK0
CK0#
V
SS
DQ14
DQ15
V
SS
V
SS
DQ20
DQ21
V
SS
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
DM2
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
DQS3#
DQS3
V
SS
DQ30
DQ31
V
SS
NC
V
DD
NC
NC
V
DD
A11
A7
A6
V
DD
A4
A2
102
A0
152
104
V
DD
154
106
BA1
156
108
RAS#
158
110
S0#
160
112
V
DD
162
114 ODT0 164
116 NC/A13 166
118
V
DD
168
120
NC
170
122
V
SS
172
124 DQ36 174
126 DQ37 176
128
V
SS
178
130
DM4
180
132
V
SS
182
134 DQ38 184
136 DQ39 186
138
V
SS
188
140 DQ44 190
142 DQ45 192
144
V
SS
194
146 DQS5# 196
148 DQS5 198
150
V
SS
200
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
CK1
CK1#
V
SS
DM6
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DQS7#
DQS7
V
SS
DQ62
DQ63
V
SS
SA0
SA1
1. Pin 85 is NC for 256MB and 512MB, BA2 for 1GB.
2. Pin 116 is NC for 256MB, A13 for 512MB and 1GB.
PDF: 09005aef80eec96e/Source: 09005aef80eec946
HTF8C32_64_128x64HG.fm - Rev. E 6/08 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB: (x64, SR) 200-Pin DDR2 SDRAM SODIMM
Module Pin Assignments and Descriptions
Table 7:
Symbol
A[15:0]
Pin Descriptions
Type
Input
Description
Address inputs:
Provide the row address for ACTIVE commands, and the column address and
auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory
array in the respective bank. A10 sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA[2/1:0]) or all
device banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE
command. A[12:0] (512MB) and A[13:0] (1GB, 2GB).
A[15:14] are connected for parity.
Bank address inputs:
BA[2/1:0] define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA[2/1:0] define which mode register (MR, EMR1,
EMR2, and EMR3) is loaded during the LOAD MODE command. BA[1:0] (512MB, 1GB) and
BA[2:0] (2GB).
Clock:
CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Output data (DQ, DQS, and DQS#) is referenced to the crossings of CK and CK#.
Clock enable:
CKE enables (registered HIGH) and disables (registered LOW) internal circuitry
and clocks on the DDR2 SDRAM.
Input data mask:
DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH, along with the input data, during a write access. DM is sampled on both edges
of DQS. Although the DM pins are input-only, DM loading is designed to match that of the DQ
and DQS pins.
On-die termination:
ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR2 SDRAM. When enabled in normal operation, ODT
is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will be
ignored if disabled via the LOAD MODE command.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being entered.
Reset:
Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can
be used during power-up to ensure that CKE is LOW and DQ are High-Z.
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs:
These pins are used to configure the SPD EEPROM address range on
the I
2
C bus.
Serial clock for SPD EEPROM:
SCL is used to synchronize communication to and from the
SPD EEPROM.
Data input/output:
Bidirectional data bus.
Data strobe:
DQS# is only used when differential data strobe mode is enabled via the LOAD
MODE command. Output with read data. Edge-aligned with read data. Input with write data.
Center-aligned with write data.
Serial data:
SDA is a bidirectional pin used to transfer addresses and data into and out of the
SPD EEPROM on the module on the I
2
C bus.
Power supply:
1.8V ±0.1V. The component V
DD
are connected to the module V
DD
.
SPD EEPROM power supply:
+1.7V to +3.6V.
Reference voltage:
V
DD
/2.
Ground.
No connect:
These pins are not connected on the module.
BA[2:0]
Input
CK[1:0]
CK#[1:0]
CKE0
DM[8:0]
Input
Input
Input
ODT0
Input
RAS#, CAS#,
WE#
RESET#
S0#
SA[1:0]
SCL
DQ[63:0]
DQS[8:0],
DQS#[8:0]
SDA
V
DD
V
DDSPD
V
REF
V
SS
NC
Input
Input
Input
Input
Input
I/O
I/O
I/O
Supply
Supply
Supply
Supply
–
PDF: 09005aef80eec96e/Source: 09005aef80eec946
HTF8C32_64_128x64HG.fm - Rev. E 6/08 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
256MB, 512MB, 1GB: (x64, SR) 200-Pin DDR2 SDRAM SODIMM
Module Pin Assignments and Descriptions
Figure 2:
S0#
DQS0#
DQS0
DM0
DM CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
Functional Block Diagram
DQS4#
DQS4
DM4
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U1
U7
DQS1#
DQS1
DM1
DM CS# DQS DQS#
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS5#
DQS5
DM5
DM CS# DQS DQS#
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U9
U3
DQS2#
DQS2
DM2
DM CS# DQS DQS#
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS6#
DQS6
DM6
DM CS# DQS DQS#
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U8
U4
DQS3#
DQS3
DM3
DM CS# DQS DQS#
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS7#
DQS7
DM7
DM CS# DQS DQS#
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U2
U6
SCL
U5
SPD/EEPROM
WP A0
A1
A2
BA[2/1:0]
A[13/12:0]
RAS#
CAS#
WE#
CKE0
ODT0
BA[2/1:0]: DDR2 SDRAM
A[13/12:0]: DDR2 SDRAM
RAS#: DDR2 SDRAM
CAS#: DDR2 SDRAM
WE#: DDR2 SDRAM
CKE0: DDR2 SDRAM
ODT0: DDR2 SDRAM
SDA
CK0
CK0#
U1, U2,
U8, U9
V
SS
SA0 SA1
V
SS
V
DDSPD
V
DD
V
REF
V
SS
SPD/EEPROM
DDR2 SDRAMs
DDR2 SDRAMs
CK1
CK1#
U3, U4,
U6, U7
DDR2 SDRAMs, SPD/EEPROM
PDF: 09005aef80eec96e/Source: 09005aef80eec946
HTF8C32_64_128x64HG.fm - Rev. E 6/08 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
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