TECHNOLOGY, INC.
MT8D132(X), MT16D232(X)
1 MEG, 2 MEG x 32 DRAM MODULES
DRAM
MODULE
FEATURES
• JEDEC- and industry-standard pinout in a 72-pin,
single-in-line memory module (SIMM)
• High-performance CMOS silicon-gate process.
• Single +5V
±10%
power supply
• All device pins are TTL-compatible
• Low power, 48mW standby; 1,824mW active, typical
(8MB)
• Refresh modes:
?
R
?
A
/
S ONLY,
?
C
?
A
/
S-BEFORE-?R
?
A
/
S (CBR)
and HIDDEN
• Multiple
?
R
?
A
/
S lines allow x16 or x32 width
• 1,024-cycle refresh distributed across 16ms
• FAST PAGE MODE (FPM) operating mode or
Extended Data-Out (EDO) PAGE MODE operating
mode
1 MEG, 2 MEG x 32
4, 8 MEGABYTE, 5V, FAST PAGE
OR EDO PAGE MODE
PIN ASSIGNMENT (Front View)
72-Pin SIMM
(DD-3) 1 Meg x 32
(DD-4) 2 Meg x 32
1
36
37
72
OPTIONS
• Timing
60ns access
70ns access (FAST PAGE MODE only)
• Packages
72 -pin SIMM
72 -pin SIMM (gold)
• Operating Modes
FAST PAGE MODE
EDO PAGE MODE
MARKING
-6
-7
M
G
Blank
X
KEY TIMING PARAMETERS
EDO Operating Mode
SPEED
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SYMBOL
V
SS
DQ1
DQ17
DQ2
DQ18
DQ3
DQ19
DQ4
DQ20
V
CC
NC
A0
A1
A2
A3
A4
A5
A6
PIN # SYMBOL PIN # SYMBOL PIN #
19
NC
37
NC
55
20
DQ5
38
NC
56
21
DQ21
39
V
SS
57
22
DQ6
40
?
C
?
A
?
S
/
0
58
23
DQ22
41
?
C
?
A
?
S
/
2
59
24
DQ7
42
?
C
?
A
?
S
/
3
60
25
DQ23
43
?
C
?
A
?
S
/
1
61
26
DQ8
44
?
R
?
A
?
S
/
0
62
27
DQ24
45 NC*/
?
R
?
A
?
S
/
1 63
28
A7
46
NC
64
29
NC
47
?
W
/
E
65
30
V
CC
48
NC
66
31
A8
49
DQ9
67
32
A9
50
DQ25
68
33 NC*/?R
?
A
?
S
/
3 51
DQ10
69
34
?
R
?
A
?
S
/
2
52
DQ26
70
35
NC
53
DQ11
71
36
NC
54
DQ27
72
SYMBOL
DQ12
DQ28
DQ13
DQ29
V
CC
DQ30
DQ14
DQ31
DQ15
DQ32
DQ16
NC
PRD1
PRD2
PRD3
PRD4
NC
V
SS
*4MB version only
110ns
60ns
26ns
30ns
17ns
13ns
FPM Operating Mode
SPEED
-6
-7
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
110ns
130ns
60ns
70ns
35ns
40ns
30ns
35ns
15ns
20ns
40ns
50ns
MT8D132(X), MT16D232(X)
DM53.pm5 – Rev. 12/95
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Technology, Inc.
TECHNOLOGY, INC.
MT8D132(X), MT16D232(X)
1 MEG, 2 MEG x 32 DRAM MODULES
followed by a column-address strobed-in by
?
C
?
A
/
S.
?
C
?
A
/
S
may be toggled-in by holding
?
R
?
A
/
S LOW and strobing-in
different column-addresses, thus executing faster memory
cycles. Returning
?
R
?
A
/
S HIGH terminates the FAST PAGE
MODE operation.
PART NUMBERS
EDO Operating Mode
PART NUMBER
MT8D132G-xx X
MT8D132M-xx X
MT16D232G-xx X
MT16D232M-xx X
xx = speed
DESCRIPTION
1 Meg x 32, EDO, Gold
1 Meg x 32, EDO, Tin/Lead
2 Meg x 32, EDO, Gold
2 Meg x 32, EDO, Tin/Lead
EDO PAGE MODE
EDO PAGE MODE, designated by the “X” version, is an
accelerated FAST PAGE MODE cycle. The primary advan-
tage of EDO is the availability of data-out even after
?
C
?
A
/
S
goes back HIGH. EDO provides for
?
C
?
A
/
S precharge time
(
t
CP) to occur without the output data going invalid. This
elimination of C
?
A
/
S output control provides for pipeline
?
READs.
FAST PAGE MODE modules have traditionally turned
the output buffers off (High-Z) with the rising edge of
?
C
?
A
/
S. EDO operates as any DRAM READ or FAST-PAGE-
MODE READ, except data will be held valid after
?
C
?
A
/
S
goes HIGH, as long as
?
R
?
A
/
S and
?
O
?
E are held LOW and
?
W
/
E
is held HIGH (reference MT4C4007J DRAM data sheet for
additional information on EDO functionality).
FPM Operating Mode
PART NUMBER
MT8D132G-xx
MT8D132M-xx
MT16D232G-xx
MT16D232M-xx
xx = speed
DESCRIPTION
1 Meg x 32, Gold
1 Meg x 32, Tin/Lead
2 Meg x 32, Gold
2 Meg x 32, Tin/Lead
GENERAL DESCRIPTION
The MT8D132(X) and MT16D232(X) are randomly ac-
cessed 4MB and 8MB solid-state memories organized in a
x32 configuration. During READ or WRITE cycles each bit
is uniquely addressed through the 20 address bits, which
are entered 10 bits (A0 -A9) at a time.
?
R
?
A
/
S is used to latch the
first 10 bits and
?
C
?
A
/
S the latter 10 bits. A READ or WRITE
cycle is selected with the W
/
E input. A logic HIGH on
?
W
/
E
?
dictates READ mode while a logic LOW on
?
W
/
E dictates
WRITE mode. During a WRITE cycle, data-in (D) is latched
by the falling edge of
?
W
/
E or
?
C
?
A
/
S, whichever occurs last.
EARLY WRITE occurs when
?
W
/
E goes LOW prior to
?
C
?
A
/
S
going LOW, the output pin(s) remain open (High-Z) until
the next
?
C
?
A
/
S cycle.
REFRESH
Returning
?
R
?
A
/
S and
?
C
?
A
/
S HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the
?
R
?
A
/
S HIGH time. Memory cell data is retained in its
correct state by maintaining power and executing any
?
R
?
A
/
S cycle (READ, WRITE) or
?
R
?
A
/
S refresh cycle (?R
?
A
/
S
ONLY, CBR or HIDDEN) so that all 1,024 combination of
?
R
?
A
/
S addresses (A0 -A9) are executed at least every 16ms,
regardless of sequence.
x16 CONFIGURATION
FAST PAGE MODE
FAST PAGE MODE operations allow faster data opera-
tions (READ or WRITE) within a row-address-defined
(A0 -A9) page boundary. The FAST PAGE MODE cycle is
always initiated with a row-address strobed-in by
?
R
?
A
/
S
For x16 applications, the corresponding DQ and
?
C
?
A
/
S
pins must be connected together (DQ1 to DQ17, DQ2 to
DQ18 and so forth, and
?
C
?
A
/
S
/
0 to
?
C
?
A
/
S
/
2 and
?
C
?
A
/
S
/
1 to
?
C
?
A
/
S
/
3). Each
?
R
?
A
/
S is then a bank select for the x16 memory
organization.
MT8D132(X), MT16D232(X)
DM53.pm5 – Rev. 12/95
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Technology, Inc.
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