HY27UG(08/16)4G(2/D)M Series
4Gbit (512Mx8bit / 256Mx16bit) NAND Flash
Document Title
4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Memory
Revision History
Revision
No.
0.0
Initial Draft.
1) Add Errata
tWH
tWP
25
35
tWC
50
60
History
Draft Date
May. 13. 2005
Remark
Preliminary
0.1
Specification
Relaxed value
15
20
May. 23. 2005
Preliminary
1) Correct the Valid Blocks Number.
0.2
Valid Blocks (max)
Before
After
4,098
4,096
Jun. 13. 2005
Preliminary
1) Add tRSBY (Table 11)
- tRSBY (Dummy Busy Time for Cache Read)
0.3
- tRSBY is 5us (typ.)
2) Edit Figure 18, 19
3) Correct Extended Read Status Register Commands (Table. 19)
1) Add ULGA Package.
- Figures & texts are added.
2) Correct the test Conditions (DC Characteristics table)
Test Conditions (
I
LI,
I
LO
)
Before
VIN=VOUT=0 to 3.6V
VIN=VOUT=0 to Vcc (max)
JUn. 14. 2005
Preliminary
0.4
After
Sep. 02. 2005
Preliminary
3) Change AC Conditions table
4) Add tWW parameter ( tWW = 100ns, min)
- Texts & Figures are added.
- tWW is added in AC timing characteristics table.
5) Edit System Interface Using CE don’t care Figures.
6) Correct Address Cycle Map.
Rev 0.7 / Feb. 2006
1
HY27UG(08/16)4G(2/D)M Series
4Gbit (512Mx8bit / 256Mx16bit) NAND Flash
Revision History
Revision
No.
History
7) Correct PKG dimension (TSOP PKG)
CP
Before
After
0.050
0.100
-Continued-
Draft Date
Remark
8) Delete the 1.8V device’s features.
9) Change DC Characteristics (Table 8)
- Operating Current
I
CC1
Typ
Before
0.4
After
20
25
Max
40
45
I
CC2
Typ
20
25
Max
40
45
I
CC3
Typ
20
25
Max
40
45
Sep. 16. 2005
Preliminary
10) Change AC Characteristics
- Errata is deleted.
tWC
Before
After
60ns
50ns
tWP
35ns
25ns
tWH
20ns
15ns
- tR is changed.
tR
Before
After
0.5
25us
30us
Oct. 05. 2005
Preliminary
1) Delete Concurrent Operation.
1) Change DC Characteristics (Table 8)
I
CC1
I
CC2
Typ
25
20
Max
45
40
I
CC3
Typ
25
20
Max
45
40
0.6
Before
After
Typ
25
20
Max
45
40
Dec. 09. 2005
2) Delete Preliminary.
Rev 0.7 / Feb. 2006
2
HY27UG(08/16)4G(2/D)M Series
4Gbit (512Mx8bit / 256Mx16bit) NAND Flash
Revision History
Revision
No.
History
1) Correct tCS parameter in Autosleep
tCS
0.7
Before
After
100ns (Min.)
40ns (Min.)
Feb. 14. 2006
-Continued-
Draft Date
Remark
Rev 0.7 / Feb. 2006
3
HY27UG(08/16)4G(2/D)M Series
4Gbit (512Mx8bit / 256Mx16bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES
- Cost effective solutions for mass storage applications
NAND INTERFACE
- x8 bus width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
STATUS REGISTER
ELECTRONIC SIGNATURE
- Manufacturer Code
- Device Code
CHIP ENABLE DON'T CARE OPTION
- Simple interface with microcontroller
AUTOMATIC PAGE 0 READ AT POWER-UP OPTION
- Boot from NAND support
- Automatic Memory Download
SERIAL NUMBER OPTION
HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions
DATA INTEGRITY
- 100,000 Program/Erase cycles
- 10 years Data Retention
PACKAGE
- HY27UG(08/16)4G2M-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27UG(08/16)4G2M-T (Lead)
- HY27UG(08/16)4G2M-TP (Lead Free)
- HY27UG(08/16)4GDM-UP
: 52-ULGA (12 x 17 x 0.65 mm)
- HY27UG(08/16)4GDM-UP (Lead Free)
SUPPLY VOLTAGE
- 3.3V device: VCC
= 2.7 to 3.6V : HY27UG(08/16)4G(2/D)M
Memory Cell Array
= (2K + 64) Bytes x 64 Pages x 4,096 Blocks
= (1K + 32) Words x 64 Pages x 4,096 Blocks
PAGE SIZE
- x8 device : (2K + 64 spare) Bytes
: HY27UG084G(2/D)M
- x16 device : (1K + 32 spare) Words
: HY27UG164G2M
BLOCK SIZE
- x8 device: (128K + 4K spare) Bytes
- x16 device: (64K + 2K spare) Words
PAGE READ / PROGRAM
- Random access: 30us (max.)
- Sequential access: 50ns (min.)
- Page program time: 200us (typ.)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
CACHE PROGRAM MODE
- Internal Cache Register to improve the program
throughput
Rev 0.7 / Feb. 2006
4
HY27UG(08/16)4G(2/D)M Series
4Gbit (512Mx8bit / 256Mx16bit) NAND Flash
1. SUMMARY DESCRIPTION
The HYNIX HY27UG(08/16)4G(2/D)M series is a 512Mx8bit with spare 16Mx8 bit capacity. The device is offered in
3.3V Vcc Power Supply.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old
data is erased.
The device contains 4096 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected
Flash cells.
A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in
typical 2ms on a 128K-byte(X8 device) block.
Data in the page mode can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and
data input/output as well as command input. This interface allows a reduced pin count and easy migration towards dif-
ferent densities, without any rearrangement of footprint.
Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin.
The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where
required, and internal verification and margining of data.
The modifying can be locked using the WP input pin.
The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multi-
ple memories the R/B pins can be connected all together to provide a global status signal.
Even the write-intensive systems can take advantage of the HY27UG(08/16)4G(2/D)M extended reliability of 100K pro-
gram/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.
Optionally the chip could be offered with the CE don’t care function. This option allows the direct download of the code
from the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation.
The copy back function allows the optimization of defective blocks management: when a page program operation fails
the data can be directly programmed in another page inside the same array section without the time consuming serial
data insertion phase.
The cache program feature allows the data insertion in the cache register while the data register is copied into the
flash array. This pipelined program operation improves the program throughput when long files are written inside the
memory.
A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when con-
secutive pages have to be streamed out.
This device includes also extra features like OTP/Unique ID area, Block Lock mechanism, Automatic Read at Power Up,
Read ID2 extension.
The HYNIX HY27UG(08/16)4G(2/D)M series is available in 48 - TSOP1 12 x 20 mm, 52-ULGA 12 x 17 mm.
1.1 Product List
PART NUMBER
HY27UG084G(2/D)M
HY27UG164G2M
ORIZATION
x8
x16
VCC RANGE
2.7 - 3.6 Volt
2.7 - 3.6 Volt
PACKAGE
48TSOP1/52-ULGA
48TSOP1
Rev 0.7 / Feb. 2006
5
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