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M2006-02AI669.1281

Description
PLL Based Clock Driver, 2 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC, LCC-36
Categorylogic    logic   
File Size408KB,8 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

M2006-02AI669.1281 Overview

PLL Based Clock Driver, 2 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC, LCC-36

M2006-02AI669.1281 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeLCC
package instruction9 X 9 MM, CERAMIC, LCC-36
Contacts36
Reach Compliance Codenot_compliant
Input adjustmentDIFFERENTIAL MUX
JESD-30 codeS-CQCC-N36
JESD-609 codee0
length8.99 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals36
Actual output times2
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeQCCN
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height3.1 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formNO LEAD
Terminal pitch0.635 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width8.99 mm
minfmax700 MHz
Integrated
Circuit
Systems, Inc.
Product Data Sheet
M2006-02A
VCSO B
ASED
FEC C
LOCK
PLL
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
FIN_SEL1
GND
NC
DIF_REF0
nDIF_REF0
REF_SEL
DIF_REF1
nDIF_REF1
VCC
FIN_SEL0
FEC_SEL0
FEC_SEL1
FEC_SEL2
FEC_SEL3
VCC
DNC
DNC
DNC
27
26
25
24
23
22
21
20
19
G
ENERAL
D
ESCRIPTION
The M2006-02A is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock frequency
translation and jitter attenuation.
The device supports both forward
and inverse FEC (Forward Error
Correction) clock multiplication
ratios. Multiplication ratios are
pin-selected from pre-programming look-up tables.
F
EATURES
Reduced intrinsic output jitter
and
improved power
supply noise rejection
compared to
M2006-02
Low phase jitter of 0.25 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
Pin-selectable PLL divider ratios support forward and
inverse FEC ratio translation, including:
• 255/238 (OTU1) Mapping and 238/255 De-mapping
• 255/237 (OTU2) Mapping and 237/255 De-mapping
• 255/236 (OTU3) Mapping and 236/255 De-mapping
28
29
30
31
32
33
34
35
36
M2006-02
A
(Top View)
18
17
16
15
14
13
12
11
10
P0_SEL
P1_SEL
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
Figure 1: Pin Assignment
Input reference and VCSO frequencies up to 700MHz,
supports loop timing modes
(Specify VCSO frequency at time of order)
Supports active switching between inverse-FEC and
non-FEC clock ratios (same VCSO center frequency)
Ideal for complex ratio FEC ratio translation and
for use with an unstable reference
(i.e., similar to the
M2006-12A
- and pin-compatible - but without the
Hitless Switching and Phase Build-out functions)
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
Example I/O Clock Combinations
Using M2006-02A-622.0800
PLL Ratio
1/1
237/255
(inverse FEC)
Input Clock (MHz)
622.08, 155.52,
77.76, or 19.44
669.3266, 167.3316,
83.6658, or 20.9165
Output Clock (MHz)
622.08
or
155.52
Table 1: Example I/O Clock Combinations Using M2006-02A-622.0800
Using M2006-02A-669.3266
PLL Ratio
237/255
(FEC rate)
1/1
Input Clock (MHz)
622.08, 155.52,
77.76, or 19.44
669.3266, 167.3316,
83.6658, or 20.9165
Output Clock (MHz)
669.3266
or
167.3316
Table 2: Example I/O Clock Combinations Using M2006-02A-669.3266
S
IMPLIFIED
B
LOCK
D
IAGRAM
Loop
Filter
M2006-02
A
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
REF_SEL
4
2
0
Rfec Div
1
Mfec Div
Mfin Div
(1, 4, 8, or 32)
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
1
2
3
4
5
6
7
8
9
VCSO
P0 Div
(1 or 4)
FOUT0
nFOUT0
FEC_SEL3:0
FIN_SEL1:0
Mfec / Rfec
Divider LUT
Mfin Divider
LUT
P0_SEL
P1 Div
(1 or 4)
FOUT1
nFOUT1
P1_SEL
Figure 2: Simplified Block Diagram
M2006-02A Datasheet Rev 1.0
M2006-02A VCSO Based FEC Clock PLL
Revised 28Jul2004
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