HY27UH088G2M-TPIP datasheet, PDF

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HY27UH088G2M-TPIP: DescriptionFlash, 1GX8, 30ns, PDSO48, 12 X 20 MM, 1.20 MM HEIGHT, LEAD FREE, TSOP1-48; Categorystorage storage; File Size437KB，53 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/; Environmental Compliance

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HY27UH088G2M-TPIP Overview

Flash, 1GX8, 30ns, PDSO48, 12 X 20 MM, 1.20 MM HEIGHT, LEAD FREE, TSOP1-48

HY27UH088G2M-TPIP Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	SK Hynix
Parts packaging code	TSOP1
package instruction	TSOP1, TSSOP48,.8,20
Contacts	48
Reach Compliance Code	unknown
ECCN code	3A991.B.1.A
Maximum access time	30 ns
command user interface	YES
Data polling	NO
JESD-30 code	R-PDSO-G48
JESD-609 code	e6
length	18.4 mm
memory density	8589934592 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of departments/size	8K
Number of terminals	48
word count	1073741824 words
character code	1000000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	1GX8
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP1
Encapsulate equivalent code	TSSOP48,.8,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
page size	2K words
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Programming voltage	3.3 V
Certification status	Not Qualified
ready/busy	YES
Maximum seat height	1.2 mm
Department size	128K
Maximum standby current	0.0002 A
Maximum slew rate	0.06 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Bismuth (Sn/Bi)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
switch bit	NO
type	SLC NAND TYPE
width	12 mm

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HY27UH088G(2/D)M Series

8Gbit (1Gx8bit) NAND Flash

Document Title

8Gbit (1Gx8bit) NAND Flash Memory

Revision History

Revision

No.

0.0

Initial Draft.

1) Add Errata

tWH

tWP

tWC

History

Draft Date

May. 13. 2005

Remark

Preliminary

0.1

Specification

Relaxed

value

May. 23. 2005

Preliminary

1) Correct the valid Blocks Number.

Valid Blocks (max)

0.2

Before

After

8,196

8,192

Jun. 13. 2005

Preliminary

1) Add tRSBY (Table11)

- tRSBY (Dummy Busy Time for Cache Read)

0.3

- tRSBY is 5us (typ.)

2) Edit figure 18, 19

3) Correct Extended Read Status Register Commands (Table. 19)

1) Add TLGA package

- Figures & texts are added.

2) Correct the test Conditions (DC Characteristics table)

Test Conditions (

LI,

)

VIN=VOUT=0 to 3.6V

Jun. 14. 2005

Preliminary

0.4

VIN=VOUT=0 to Vcc (max)

Sep. 16. 2005

Preliminary

3) Change AC Conditions table

4) Add tWW parameter ( tWW = 100ns, min)

- Texts & Figures are added.

- tWW is added in AC timing characteristics table.

5) Edit System Interface Using CE don’t care Figures.

6) Correct Address Cycle Map.

Rev 0.7 / Feb. 2006

HY27UH088G(2/D)M Series

8Gbit (1Gx8bit) NAND Flash

1. SUMMARY DESCRIPTION

The HYNIX HY27UH088G(2/D)M series is a 1Gx8bit with spare 32Mx8 bit capacity. The device is offered in 3.3V Vcc

Power Supply.

Its NAND cell provides the most cost-effective solution for the solid state mass storage market.

The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old

data is erased.

The device contains 8192 blocks, composed by 64 pages consisting in two NAND structures of 32 series connected

Flash cells.

A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in

typical 2ms on a 128K-byte(X8 device) block.

Data in the page mode can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and

data input/output as well as command input. This interface allows a reduced pin count and easy migration towards dif-

ferent densities, without any rearrangement of footprint.

Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin.

The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where

required, and internal verification and margining of data.

The modifying can be locked using the WP input pin.

The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multi-

ple memories the R/B pins can be connected all together to provide a global status signal.

Even the write-intensive systems can take advantage of the HY27UH088G(2/D)M extended reliability of 100K program/

erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm.

Optionally the chip could be offered with the CE don’t care function. This option allows the direct download of the code

from the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation.

The copy back function allows the optimization of defective blocks management: when a page program operation fails

the data can be directly programmed in another page inside the same array section without the time consuming serial

data insertion phase.

The cache program feature allows the data insertion in the cache register while the data register is copied into the

flash array. This pipelined program operation improves the program throughput when long files are written inside the

memory.

A cache read feature is also implemented. This feature allows to dramatically improve the read throughput when con-

secutive pages have to be streamed out.

This device includes also extra features like OTP/Unique ID area, Block Lock mechanism, Automatic Read at Power Up,

Read ID2 extension.

The HYNIX HY27UH088G(2/D)M series is available in 48 - TSOP1 12 x 20 mm, 52-TLGA 12 x 17mm.

1.1 Product List

PART NUMBER

HY27UH088G(2/D)M

ORIZATION

VCC RANGE

2.7V - 3.6 Volt

PACKAGE

48TSOP1 / 52-TLGA

Rev 0.7 / Feb. 2006

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