TE –
SOLE
– OB
8 P-Channel Latchable Power MOSFET Array
Ordering Information
V
DD
(max)
-320V
R
O(ON)
(max)
700Ω
I
O(ON)
(min)
-15mA
I
O(OFF)
(max)
-1.0nA
Order Number/Package
SO-16
AP0332CG
Die
AP0332ND
AP0332
*Average current per channel, measured with all eight channels connected in parallel.
Features
Low drain to source leakage
Interfaces directly to TTL and CMOS logic
8 independent channels
Low crosstalk between channels
Low power dissipation
Freedom from secondary breakdown
Serial data input
On-chip decoder, latch with set and write disable circuitry
General Description
The Supertex AP0332 is an 8 P-Channel 320V common source
power MOSFET array with a CMOS 8 bit addressable latch. The
outputs are guaranteed to have very low leakage current. The
outputs are addressed by logic inputs A0, A1, and A2. The
addressed and unaddressed output can be turned on or off by the
data, set, and write disable inputs.
The AP0332 is ideally suited for low leakage/high impedance
measurements, providing excellent accuracy as well as resolution
for automatic bare board test equipment and other applications.
9
Applications
High impedance/low leakage measurements
for bare board testers
High voltage piezoelectric transducer drivers
High voltage electroluminescent panel drivers
High voltage electrostatic array drivers
General multi-channel driver arrays
Q
7
Set
Data
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Pin Configuration
V
DD
Q
6
Q
5
Q
4
Q
3
Q
2
Q
1
Q
0
Absolute Maximum Ratings
Off-state output voltage, V
OO
Logic supply voltage, V
DD
Logic input levels, all inputs
Operating and storage temperature range
Soldering temperature
2
Channel-to-channel crosstalk
Notes:
1. All voltages are referenced to V
SS
.
2. Distance of 1.6mm from case for 10 seconds.
1
-320V
Write Dis
A
0
A
1
A
2
V
SS
-0.5V to +15V
-0.5V to V
DD
-55°C to +150°C
300°C
10mV/V
top view
SO-16
Note: See Package Outline section for dimensions.
9-5
AP0332
Electrical Characteristics
(@ 25°C and V
DC Characteristics
Symbol
I
O(OFF)
I
O(ON)
R
O(ON)
∆R
O(ON)
I
DDQ
V
IL
V
IH
I
IN
Parameter
Off-State Output Current
On-State Output Current
On-State Output Resistance
Change in R
O(ON)
with High Temperature
Quiescent Logic Supply Current
Input Low Voltage
Input High Voltage
Input Current
DD
= 12V unless otherwise specified)
Typ
Max
-8.0
Unit
nA
mA
700
0.8
0.05
16.5
3.5
Ω
%/°C
µA
V
V
1.0
µA
Conditions
V
O
= max. rating,
8 outputs connected in parallel
V
O
= 25V
I
O
= -10mA
I
O
= -10mA
Min
-15
12
Note:
1. All voltages are referenced to V
SS
.
AC Characteristics
Symbol
t
D(ON)
t
D(OFF)
t
r
t
f
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PHL
, t
PLH
t
W
t
W
t
W
t
S
t
H
C
IN
Parameter
Turn-On Delay Time
Turn-Off Delay Time
Rise Time
Fall Time
TE –
SOLE
– OB
Min
Typ
800
800
200
200
87
87
107
50
100
40
50
75
5.0
7.5
100
200
75
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
Fig. 1*
1a
1b
10
11
2
3
9
4
8
5
6
7
Conditions
Propagation Delay Time
from Write Disable to Output
Propagation Delay Time
from Set to Output
Propagation Delay Time
from Address to Output
Minimum Pulse Width – Data
Minimum Pulse Width – Address
Minimum Pulse Width – Set
Setup Time – Data to Write Disable
Hold Time – Data to Write Disable
Input capacitance – Any Input
V
O
= 25V, I
O
= -10mA
*Refer to circled numbers on Timing Diagram (Figure 1).
Note:
1. All voltages are referenced to V
SS
.
9-6
AP0332
Recommended Operating Conditions
(For maximum reliability, nominal operating conditons should be selected so that operation is always within the following ranges.)
Symbol
V
DD
V
O
V
IH
V
IL
T
A
Parameter
Logic supply voltage
Output Voltage referenced to V
DD
Input High Voltage
Input Low Voltage
Operating Free-Air Temperature
12V
12V
V
DD
Min
10.0
0
V
DD
- 2
0
0
Max
13.2
-320
V
DD
2.0
70
Unit
V
V
V
V
°C
Note:
1. All voltages are referenced to V
SS
.
Mode Selection
Data
H
L
H
L
H
L
H
L
TE –
SOLE
– OB
Write Disable
L
H
L
H
Set
L
L
H
H
Addressed Output
Off
On
Holdspriv.
Off
On
Off
Unaddressed Outputs
Holdspriv.
Holdspriv.
Off
Off
9
Timing Diagram
A
0
, A
1
, A
2
t
W
8
Write Disable
Data
t
W
Set
Q
0
ON
Q
0
OFF
Q
7
ON
Q
7
OFF
1b
t
d(OFF)
t
R
10
t
P
3
t
f
11
t
P
9
t
d(ON)
1a
t
P
2
5
t
W
4
t
S
6
t
H
7
Figure 1
9-7
AP0332
Functional Block Diagram
Data
Write Disable
ETE –
SOL
– OB
V
DD
(+)
S
Latch
Q
7
Latch
Q
6
Latch
A
0
Latch
A
1
3:8
Decoder
Latch
A
2
Latch
Q
5
Q
4
Q
3
Q
2
Latch
Q
1
Latch
Q
0
Set
V
SS
(–)
9-8
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