INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4060
14-stage binary ripple counter with
oscillator
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
14-stage binary ripple counter with oscillator
FEATURES
•
All active components on chip
•
RC or crystal oscillator configuration
•
Output capability: standard (except for R
TC
and C
TC
)
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4060 are high-speed Si-gate CMOS
devices and are pin compatible with “4060” of the “4000B”
series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4060 are 14-stage ripple-carry
counter/dividers and oscillators with three oscillator
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT4060
terminals (RS, R
TC
and C
TC
), ten buffered outputs (Q
3
to
Q
9
and Q
11
to Q
13
) and an overriding asynchronous
master reset (MR).
The oscillator configuration allows design of either RC or
crystal oscillator circuits. The oscillator may be replaced by
an external clock signal at input RS. In this case keep the
other oscillator pins (R
TC
and C
TC
) floating.
The counter advances on the negative-going transition of
RS. A HIGH level on MR resets the counter (Q
3
to Q
9
and
Q
11
to Q
13
= LOW), independent of other input conditions.
In the HCT version, the MR input is TTL compatible, but
the RS input has CMOS input switching levels and can be
driven by a TTL output by using a pull-up resistor to V
CC
.
TYPICAL
SYMBOL PARAMETER
t
PHL/
t
PLH
propagation delay
RS to Q
3
Q
n
to Q
n+1
t
PHL
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
3. For formula on dynamic power dissipation see next pages.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
MR to Q
n
maximum clock frequency
input capacitance
power dissipation capacitance per package
notes 1, 2 and 3
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
31
6
17
87
3.5
40
31
6
18
88
3.5
40
ns
ns
ns
MHz
pF
pF
HCT
UNIT
December 1990
2
Philips Semiconductors
Product specification
14-stage binary ripple counter with oscillator
DYNAMIC POWER DISSIPATION FOR 74HC
PARAMETER
total dynamic power
dissipation when using the
on-chip oscillator (P
D
)
Note
1. GND = 0 V; T
amb
= 25
°C
DYNAMIC POWER DISSIPATION FOR 74HCT
PARAMETER
total dynamic power
dissipation when using the
on-chip oscillator (P
D
)
Notes
1. GND = 0 V; T
amb
= 25
°C
2. Where: f
o
= output frequency in MHz
f
osc
= oscillator frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
C
t
= timing capacitance in pF
V
CC
= supply voltage in V
V
CC
(V)
4.5
TYPICAL FORMULA FOR P
D
(µW) (note
1)
V
CC
(V) TYPICAL FORMULA FOR P
D
(µW) (note
1)
2.0
4.5
6.0
74HC/HCT4060
C
PD
×
f
osc
×
V
CC2
+ ∑
(C
L
×
V
CC2
×
f
o
)
+
2C
t
×
V
CC2
×
f
osc
+
60
×
V
CC
2
+ ∑
(C
×
V
2
×
f )
+
2C
×
V
2
×
f
C
PD
×
f
osc
×
V
CC
L
CC
o
t
CC
osc
+
1 750
×
V
CC
2
+ ∑
(C
×
V
2
×
f )
+
2C
×
V
2
×
f
C
PD
×
f
osc
×
V
CC
L
CC
o
t
CC
osc
+
3 800
×
V
CC
C
PD
×
f
osc
×
V
CC2
+ ∑
(C
L
×
V
CC2
×
f
o
)
+
2C
t
×
V
CC2
×
f
osc
+
1 750
×
V
CC
Fig.4 Functional diagram.
APPLICATIONS
•
Control counters
•
Timers
•
Frequency dividers
•
Time-delay circuits
December 1990
4
DSP and ARM Processors
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