FINAL
Am28F256A
256 Kilobit (32,768 x 8-Bit) CMOS 12.0 Volt, Bulk Erase
Flash Memory with Embedded Algorithms
DISTINCTIVE CHARACTERISTICS
s
High performance
— 70 ns maximum access time
s
CMOS low power consumption
— 30 mA maximum active current
— 100
µA
maximum standby current
— No data retention power consumption
s
Compatible with JEDEC-standard byte-wide
32-Pin EPROM pinouts
— 32-pin PDIP
— 32-pin PLCC
— 32-pin TSOP
— 32-pin LCC
s
100,000 write/erase cycles minimum
s
Write and erase voltage 12.0 V
±5%
s
Latch-up protected to 100 mA from –1 V to
V
CC
+1 V
Advanced
Micro
Devices
s
Embedded Erase Electrical Bulk Chip-Erase
— 1.5 seconds typical chip-erase including
pre-programming
s
Embedded Program
— 14
µs
typical byte-program including time-out
— 0.5 second typical chip program
s
Command register architecture for
microprocessor/microcontroller compatible
write interface
s
On-chip address and data latches
s
Advanced CMOS flash memory technology
— Low cost single transistor memory cell
s
Embedded algorithms for completely
self-timed write/erase operations
GENERAL DESCRIPTION
The Am28F256A is a 256K Flash memory organized as
32K bytes of 8 bits each. AMD’s Flash memories offer
the most cost-effective and reliable read/write non- vola-
tile random access memory. The Am28F256A is pack-
aged in 32-pin PDIP, PLCC, and TSOP versions. It is
designed to be reprogrammed and erased in-system or
in standard EPROM programmers. The Am28F256A is
erased when shipped from the factory.
The standard Am28F256A offers access times as fast
as 70 ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the Am28F256A has separate chip enable (CE) and out-
put enable (OE) controls.
AMD’s Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F256A uses a command register to manage this
functionality, while maintaining a standard JEDEC
Flash Standard 32-pin pinout. The command register al-
lows for 100% TTL level control inputs and fixed power
supply levels during erase and programming.
AMD’s Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles. The
AMD cell is designed to optimize the erase and
programming mechanisms. In addition, the combination
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of advanced tunnel oxide processing and low internal
electric fields for erase and programming operations
produces reliable cycling. The Am28F256A uses a
12.0 V
±
5% V
PP
high voltage input to perform the erase
and programming functions.
The highest degree of latch-up protection is achieved
with AMD’s proprietary non-epi process. Latch-up pro-
tection is provided for stresses up to 100 milliamps on
address and data pins from –1 V to V
CC
+1 V.
Embedded Program
The Am28F256A is byte programmable using the
Embedded Programming algorithm. The Embedded
Programming algorithm does not require the system to
time-out or verify the data programmed. The typical
room temperature programming time of the
Am28F256A is one half second.
Embedded Erase
The entire chip is bulk erased using the Embedded
Erase algorithm. The Embedded Erase algorithm auto-
matically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
controlled internal to the device. Typical erasure at room
Publication#
18879
Rev.
B
Amendment
/0
Issue Date:
November 1995
AMD
temperature is accomplished in 1.5 seconds, including
preprogramming.
AMD’s Am28F256A is entirely pin and software
compatible with AMD’s Am28F020A, Am28F010A and
Am28F512A Flash memories.
Embedded Programming Algorithm vs.
Flashrite Programming Algorithm
The Flashrite Programming algorithm requires the user
to write a program set-up command, a program com-
mand (program data and address), and a program verify
command followed by a read and compare operation.
The user is required to time the programming pulse
width in order to issue the program verify command. An
integrated stop timer prevents any possibility of over-
programming. Upon completion of this sequence the
data is read back from the device and compared by the
user with the data intended to be written; if there is not a
match, the sequence is repeated until there is a match or
the sequence has been repeated 25 times.
AMD’s Embedded Programming algorithm requires the
user to only write a program set-up command and a pro-
gram command (program data and address). The
device automatically times the programming pulse
width, provides the program verify and counts the
number of sequences. A status bit,
Data
Polling, pro-
vides feedback to the user as to the status of the
programming operation.
Embedded Erase Algorithm vs. Flasherase Erase
Algorithm
The Flasherase Erase algorithm requires the device to
be completely programmed prior to executing an erase
command. To invoke the erase operation the user writes
an erase set-up command, an erase command, and an
erase verify command. The user is required to time the
erase pulse width in order to issue the erase verify
command. An integrated stop timer prevents any possi-
bility of overerasure. Upon completion of this sequence
the data is read back from the device and compared by
the user with erased data. If there is not a match, the
sequence is repeated until there is a match or the
sequence has been repeated 1,000 times.
AMD’s Embedded Erase algorithm requires the user to
only write an erase set-up command and erase com-
mand. The device will automatically pre-program and
verify the entire array. Then the device automatically
times the erase pulse width, provides the erase verify
and counts the number of sequences. A status bit,
Data
Polling, provides feedback to the user as to the status of
the erase operation.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as inputs to an internal state-machine which
controls the erase and programming circuitry. During
write cycles, the command register internally latches ad-
dress and data needed for the programming and erase
operations. For system design simplification, the
Am28F256A is designed to support either
WE
or
CE
controlled writes. During a system write cycle, ad-
dresses are latched on the falling edge of
WE
or
CE
whichever occurs last. Data is latched on the rising edge
of
WE
or
CE
whichever occurs first. To simplify the fol-
lowing discussion, the
WE
pin is used as the write cycle
control pin throughout the rest of this text. All setup and
hold times are with respect to the
WE
signal.
AMD’s Flash technology combines years of EPROM
and EEPROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The
Am28F256A electrically erases all bits simultaneously
using Fowler-Nordheim tunneling. The bytes are pro-
grammed one byte at a time using the EPROM program-
ming mechanism of hot electron injection.
Am28F256A
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