Features
•
Fast 5V Read Access Time - 35 ns
•
Command Table Architecture
•
•
•
•
•
•
•
•
– Internal Program Control and Timer
12V Program and Erase
– Fast Chip Erase Time - 0.5 Second Maximum
– Word-by-word Programming - 20 µs/Word Typical
Hardware Data Protection
Low-power CMOS Operation
– 100 µA Maximum Standby
– 30 mA Maximum Active at 5 MHz
JEDEC Standard Packages
– 44-lead PLCC
– 40-lead VSOP (10 mm x 14 mm)
Pin-compatible with Atmel’s AT27C1024 and AT49F1024/1025
High-reliability CMOS Technology
– 2000V ESD Protection
– 200 mA Latchup Immunity
CMOS and TTL Compatible Inputs and Outputs
100 Write Cycles Guaranteed
1-megabit
(64K x 16)
Rewriteable
PROM
AT27RW1024
Description
The AT27RW1024 is a low-power, high-performance 1,048,576-bit electrically-
rewriteable programmable read-only memory (RWPROM) organized 64K x 16 bits. It
requires only one 5V power supply in normal read mode operation. Any word can be
accessed in less than 35 ns, eliminating the need for speed reducing WAIT states.
(continued)
Pin Configurations
Pin Name
A0 - A15
CE
OE
WE
I/O0 - I/O15
NC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
A9
A10
A11
A12
A13
A14
A15
NC
WE
VCC
VPP
CE
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VSOP Type 1
10 x 14 mm
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
PLCC Top View
I/O13
I/O14
I/O15
CE
VPP
NC
VCC
WE
NC
A15
A14
I/O3
I/O2
I/O1
I/O0
OE
NC
A0
A1
A2
A3
A4
18
19
20
21
22
23
24
25
26
27
28
I/O12
I/O11
I/O10
I/O9
I/O8
GND
NC
I/O7
I/O6
I/O5
I/O4
7
8
9
10
11
12
13
14
15
16
17
6
5
4
3
2
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A13
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
Rev. 1415A–06/99
1
The x16 organization makes this part ideal for high-
performance 16- and 32-bit DSP and microprocessor
systems. The AT27RW1024 is pin-compatible with Atmel’s
AT49F1024/1025 and AT27C1024. In read mode, the
AT27RW1024 typically consumes 15 mA. Standby mode
supply current is typically less than 10 µA. Reprogramming
the AT27RW1024 is performed by erasing the entire chip
and then programming on a word-by-word basis. The
program and erase functions are performed with V
CC
= 5V
and V
PP
= 12V. Programming time is 20 µs per word typi-
cal. 100 program and erase cycles are guaranteed.
Block Diagram
VCC
GND
OE
WE
CE
DATA INPUTS/OUTPUTS
I/O15 - I/O0
16
OE, CE, AND WE
LOGIC
DATA LATCH
INPUT/OUTPUT
BUFFERS
Y-GATING
MAIN MEMORY
(64K WORDS)
Y DECODER
ADDRESS
INPUTS
X DECODER
Device Operation
READ:
When CE and OE are low and WE is high, the data
stored at the memory location determined by the address
pins is asserted on the outputs. The outputs are put in the
high impedance state whenever CE or OE is high. This
dual-line control gives designers flexibility in preventing bus
contention.
CHIP ERASE:
The chip erase will erase all words to an
FFFFH. The chip erase command is a six bus cycle opera-
tion. The address (5555H) is latched on the falling edge of
the sixth cycle while the 10H data input is latched on the
rising edge of WE. The chip erase starts after the rising
edge of WE of the sixth cycle. Please see “Chip Erase
Cycle Waveforms” on page 7. The chip erase operation is
internally controlled; it will automatically time to completion.
After a chip erase, the device will return to the read mode.
Chip erase requires V
CC
= 5V and V
PP
= 12V.
WORD PROGRAMMING:
Once the memory array is
erased, the device is programmed (to a logical “0”) on a
word-by-word basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can
convert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified t
BP
cycle
time. Programming requires V
PP
= 12V and V
CC
= 5V.
PRODUCT IDENTIFICATION:
The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
HARDWARE DATA PROTECTION:
Hardware features
protect against inadvertent programs to the AT27RW1024
in the following ways: (a) V
CC
sense: if V
CC
is below 3.8V
(typical), the program function is inhibited. (b) Program
inhibit: holding any one of OE low, CE high or WE high
inhibits program cycles. (c) Noise filter: Pulses of less than
15 ns (typical) on the WE or CE inputs will not initiate a
program cycle.
2
AT27RW1024
AT27RW1024
Command Definition (in Hex)
Command
Sequence
Read
Chip Erase
Word Program
Product ID Entry
Product ID Exit
Note:
Bus
Cycles
1
6
4
3
1
1st Bus
Cycle
Addr
Addr
5555
5555
5555
xxxx
Data
D
OUT
AA
AA
AA
F0
2AAA
2AAA
2AAA
55
55
55
5555
5555
5555
80
A0
90
5555
Addr
AA
D
IN
2AAA
55
5555
10
2nd Bus
Cycle
Addr
Data
3rd Bus
Cycle
Addr
Data
4th Bus
Cycle
Addr
Data
5th Bus
Cycle
Addr
Data
6th Bus
Cycle
Addr
Data
The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex).
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
3
Microchip MCU
京公网安备 11010802033920号
EEWORLD
