V55C1128164MCI9 datasheet, PDF

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V55C1128164MCI9: DescriptionSynchronous DRAM, 8MX16, 7ns, CMOS, PDSO54, 0.400 INCH, GREEN, PLASTIC, TSOP2-54; Categorystorage storage; File Size621KB，48 Pages; ManufacturerProMOS Technologies Inc

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V55C1128164MCI9 Overview

Synchronous DRAM, 8MX16, 7ns, CMOS, PDSO54, 0.400 INCH, GREEN, PLASTIC, TSOP2-54

V55C1128164MCI9 Parametric

Parameter Name	Attribute value
Maker	ProMOS Technologies Inc
Parts packaging code	TSOP2
package instruction	TSOP2,
Contacts	54
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	7 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PDSO-G54
length	22.38 mm
memory density	134217728 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	54
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.95 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
width	10.16 mm

V55C1128164MCI9 Preview

V55C1128164MC

128Mbit MOBILE SDRAM

1.8 VOLT, TSOP II / FBGA PACKAGE

8M X 16

System Frequency (f

)

Clock Cycle Time (t

CK3

)

Clock Access Time (t

AC3

) CAS Latency = 3

133 MHz

7.5ns

6.0 ns

111 MHz

9.0 ns

7.0 ns

100MHz

10 ns

8.0ns

Features

■

4 banks x 2Mbit x 16 organization

■

High speed data transfer rates up to 133 MHz

■

Full Synchronous Dynamic RAM, with all signals

referenced to clock rising edge

■

Single Pulsed RAS Interface

■

Data Mask for Read/Write Control

■

Four Banks controlled by BA0 & BA1

■

Programmable CAS Latency:1, 2, 3

■

Programmable Wrap Sequence: Sequential or

Interleave

■

Programmable Burst Length:

1, 2, 4, 8, Full page for Sequential Type

1, 2, 4, 8 for Interleave Type

■

Multiple Burst Read with Single Write Operation

■

Automatic and Controlled Precharge Command

■

Random Column Address every CLK (1-N Rule)

■

Power Down Mode and Clock Suspend Mode

■

Auto Refresh and Self Refresh

■

Refresh Interval:

4096 cycles/64 ms [ 0 to 70

°C

(Commercial)] ;

4096 cycles/64ms[-40 to 85

°C

(Industrial)];

4096 cycles/44ms [-40 to 125°C

(Extended)]

■

Available in 54-ball FBGA (with 9x6 ball array

with 3 depopulated rows, 8x8 mm), and 54 pin

TSOP II

■

VDD=1.8V, VDDQ=1.8V

LVCMOS Interface

Drive Strength (DS) Option: Full, 1/2, 1/4 and 1/8

Auto Temperature Compensated Self Refresh

(Auto TCSR)

Partial Array Self Refresh (PASR) option: Full,

1/2, 1/4, 1/8 and 1/16

Deep Power Down (DPD) mode

Programmable Power Reduction Feature by par-

tial array activation during Self-Refresh

Operating Temperature Range

Commercial (0°C to 70°C)

Industrial (-40°C to +85°C)

Extended(-40°C to +125°C)

Device Usage Chart

Operating

Temperature

Range

0°C to 70°C

-40°C to 85°C

-40°C to 125°C

Package Outline

K/I

•

Access Time (ns)

•

Temperature

Mark

note: When temperature is higher than 100°C, TCSR and self-refresh is not guaranteed.

V55C1128164MC Rev. 1.1 July 2007

ProMOS TECHNOLOGIES

Part Number Information

V55C1128164MC

ProMOS

5 5

1 2 8 1 6

ORGANIZATION

& REFRESH

1Mx16, 2K : 1616

4Mx16, 4K : 6516

7 5

OTHER

: CL2

TYPE

54 : SDRAM

55 : MOBILE SDRAM

32Mx4, 4K : 12840

16Mx8, 4K : 12880

64Mx4, 8K : 25640

32Mx8, 8K : 25680

128Mx4, 8K : 51240

64Mx8, 8K : 51280

8Mx16, 4K : 12816

BLANK: CL3

TEMPERATURE

BLANK: 0 - 70C

16Mx16, 8K : 25616

32Mx16, 8K : 51216

-40 - 85C

-40 - 125C

CMOS

BANKS

VOLTAGE

2 : 2 BANKS

4 : 4 BANKS

8 : 8 BANKS

REV LEVEL

A: 1st

B: 2nd

C: 3rd

D: 4th

PACKAGE

LEAD

PLATING

GREEN PACKAGE

DESCRIPTION

TSOP

60-Ball FBGA

54-BallFBGA

BGA

Die-stacked TSOP

Die-stacked FBGA

I/O

M: LVCMOS

SPEED

10 : 100MHz

8 : 125MHz

75 : 133MHz

7 : 143MHz

6 : 166MHz

5 : 200MHz

3.0V

3.3 V

2.5 V

1.8 V

SPECIAL FEATURE

L : LOW POWER GRADE

U : ULTRA LOW POWER GRADE

* RoHS: Restriction of Hazardous Substances

* Green: RoHS-compliant and Halogen-free

V55C1128164MC Rev. 1.1 July 2007

ProMOS TECHNOLOGIES

V55C1128164MC

Description

FBGA

Pkg.

Ball Count

60 Pin WBGA PIN CONFIGURATION

Top View

Pin Configuration for x16 devices:

VDD

DQ1

DQ3

DQ5

VSS DQ15 VSSQ

DQ14 DQ13 VDDQ

DQ12 DQ11 VSSQ

DQ10 DQ9 VDDQ

DQ8

VSS

CKE

VDDQ DQ0

VSSQ DQ2

VDDQ DQ4

VSSQ DQ6

VDD LDQM DQ7

CAS

BA0

RAS

BA1

A10

VDD

UDQM CLK

VSS

A11

< Top-view >

V55C1128164MC Rev.1.1 July 2007

ProMOS TECHNOLOGIES

V55C1128164MC

Description

TSOP-II

Pkg.

Pin Count

54 Pin Plastic TSOP-II

PIN CONFIGURATION

Top View

I/O

CCQ

I/O

SSQ

I/O

CCQ

I/O

SSQ

I/O

LDQM

CAS

RAS

BA0

BA1

Pin Names

CLK

CKE

Clock Input

Clock Enable

Chip Select

Row Address Strobe

Column Address Strobe

Write Enable

Address Inputs

Bank Select

Data Input/Output

Data Mask

Power (+1.8V)

Ground

Power for I/O’s (+1.8V)

Ground for I/O’s

Not connected

I/O

SSQ

I/O

CCQ

I/O

SSQ

I/O

CCQ

I/O

UDQM

CLK

CKE

A11

RAS

CAS

–A

BA0, BA1

I/O

–I/O

LDQM, UDQM

CCQ

SSQ

V55C1128164MC Rev. 1.1 July 2007

ProMOS TECHNOLOGIES

Description

V55C1128164MC

The V55C1128164MC is a four bank Synchronous DRAM organized as 4 banks x 2Mbit x 16. The

V55C1128164MC achieves high speed data transfer rates up to 133 MHz by employing a chip architecture

that prefetches multiple bits and then synchronizes the output data to a system clock.

All of the control, address, data input and output circuits are synchronized with the positive edge of an ex-

ternally supplied clock.

Operating the four memory banks in an interleaved fashion allows random access operation to occur at

higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 133 MHz is

possible depending on burst length, CAS latency and speed grade of the device.

Signal Pin Description

CLK

Type

Input

Signal

Pulse

Polarity

Positive

Edge

Function

The system clock input. All of the SDRAM inputs are sampled on the rising edge of the

clock.

CKE

Input

Level

Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby

initiates either the Power Down mode or the Self Refresh mode.

Active Low CS enables the command decoder when low and disables the command decoder when

high. When the command decoder is disabled, new commands are ignored but previous

operations continue.

Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the

command to be executed by the SDRAM.

—

During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)

when sampled at the rising clock edge.

During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)

when sampled at the rising clock edge.CAn depends from the SDRAM organization:

• 8M x 16 SDRAM CA0–CA8.

In addition to the column address, A10(=AP) is used to invoke autoprecharge operation

at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and

BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.

During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1

to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are

used to define which bank to precharge.

Input

Pulse

RAS, CAS

A0 - A11

Input

Pulse

Input

Level

BA0,

BA1

DQx

Input

Level

—

Selects which bank is to be active.

Input

Output

Input

Level

—

Data Input/Output pins operate in the same manner as on conventional DRAMs.

LDQM

UDQM

Pulse

Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sam-

pled high. In Read mode, DQM has a latency of two clock cycles and controls the output

buffers like an output enable. In Write mode, DQM has a latency of zero and operates as

a word mask by allowing input data to be written if it is low but blocks the write operation

if DQM is high.

Power and ground for the input buffers and the core logic.

VCC, VSS

VCCQ

VSSQ

Supply

—

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

V55C1128164MC Rev. 1.1 July 2007

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