MT48LC2M32B2B5-5:G datasheet, PDF

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MT48LC2M32B2B5-5:G: DescriptionSynchronous DRAM, 2MX32, 4.5ns, CMOS, PBGA90, 8 X 13 MM, LEAD FREE, VFBGA-90; Categorystorage storage; File Size4MB，80 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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MT48LC2M32B2B5-5:G Overview

Synchronous DRAM, 2MX32, 4.5ns, CMOS, PBGA90, 8 X 13 MM, LEAD FREE, VFBGA-90

MT48LC2M32B2B5-5:G Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Micron Technology
Parts packaging code	BGA
package instruction	VFBGA, BGA90,9X15,32
Contacts	90
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	4.5 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PBGA-B90
JESD-609 code	e1
length	13 mm
memory density	67108864 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	90
word count	2097152 words
character code	2000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2MX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Encapsulate equivalent code	BGA90,9X15,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	4096
Maximum seat height	1 mm
self refresh	YES
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.002 A
Maximum slew rate	0.28 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	8 mm

MT48LC2M32B2B5-5:G Preview

64Mb: x32 SDRAM

Features

SDR SDRAM

MT48LC2M32B2 – 512K x 32 x 4 Banks

Features

• PC100-compliant

• Fully synchronous; all signals registered on positive

edge of system clock

• Internal pipelined operation; column address can

be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto precharge, includes concurrent auto precharge

and auto refresh modes

• Self refresh mode (not available on AT devices)

• Auto refresh

– 64ms, 4096-cycle refresh

(commercial and industrial)

– 16ms, 4096-cycle refresh

(automotive)

• LVTTL-compatible inputs and outputs

• Single 3.3V ±0.3V power supply

• Supports CAS latency (CL) of 1, 2, and 3

Options

• Configuration

– 2 Meg x 32 (512K x 32 x 4 banks)

• Plastic package – OCPL

– 86-pin TSOP II (400 mil) standard

– 86-pin TSOP II (400 mil) Pb-free

– 90-ball VFBGA (8mm x 13mm) Pb-

free

• Timing – cycle time

– 5ns (200 MHz)

– 5.5ns (183 MHz)

– 6ns (167 MHz)

– 7ns (143 MHz)

• Operating temperature range

– Commercial (0˚C to +70˚C)

– Industrial (–40˚C to +85˚C)

– Automotive (–40˚C to +105˚C)

• Revision

Notes:

Off-center parting line.

Available only on revision G.

Available only on revision J.

Contact Micron for availability.

Marking

2M32B2

-5

-55

-6A

-6

-7

None

:G/:J

Table 1: Key Timing Parameters

CL = CAS (READ) latency

Speed Grade

-5

-55

-6A

-6

-7

Clock

Frequency (MHz)

200

183

167

143

Target

RCD-

RP-CL

3-3-3

RCD

(ns)

CL (ns)

16.5

PDF: 09005aef811ce1fe

64mb_x32_sdram.pdf - Rev. T 04/13 EN

Products and specifications discussed herein are subject to change by Micron without notice.

Micron Technology, Inc. reserves the right to change products or specifications without notice.

64Mb: x32 SDRAM

Features

Table 2: Address Table

Parameter

Configuration

Refresh count

Row addressing

Bank addressing

Column addressing

2 Meg x 32

512K x 32 x 4 banks

2K A[10:0]

4 BA[1:0]

256 A[7:0]

Table 3: 64Mb (x32) SDR Part Numbering

Part Numbers

MT48LC2M32B2TG

MT48LCM32B2P

MT48LC2M3B2B5

Note:

Architecture

2 Meg x 32

Package

86-pin TSOP II

90-ball VFBGA

1. FBGA Device Decoder:

www.micron.com/decoder.

PDF: 09005aef811ce1fe

64mb_x32_sdram.pdf - Rev. T 04/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

64Mb: x32 SDRAM

Features

Contents

General Description ......................................................................................................................................... 7

Automotive Temperature .............................................................................................................................. 7

Functional Block Diagrams ............................................................................................................................... 8

Pin and Ball Assignments and Descriptions ....................................................................................................... 9

Package Dimensions ....................................................................................................................................... 12

Temperature and Thermal Impedance ............................................................................................................ 14

Electrical Specifications .................................................................................................................................. 17

Electrical Specifications – I

Parameters ........................................................................................................ 19

Electrical Specifications – AC Operating Conditions ......................................................................................... 21

Functional Description ................................................................................................................................... 24

Commands .................................................................................................................................................... 25

COMMAND INHIBIT .................................................................................................................................. 25

NO OPERATION (NOP) ............................................................................................................................... 26

LOAD MODE REGISTER (LMR) ................................................................................................................... 26

ACTIVE ...................................................................................................................................................... 26

READ ......................................................................................................................................................... 27

WRITE ....................................................................................................................................................... 28

PRECHARGE .............................................................................................................................................. 29

BURST TERMINATE ................................................................................................................................... 29

REFRESH ................................................................................................................................................... 30

AUTO REFRESH ..................................................................................................................................... 30

SELF REFRESH ....................................................................................................................................... 30

Truth Tables ................................................................................................................................................... 31

Initialization .................................................................................................................................................. 36

Mode Register ................................................................................................................................................ 38

Burst Length .............................................................................................................................................. 40

Burst Type .................................................................................................................................................. 40

CAS Latency ............................................................................................................................................... 42

Operating Mode ......................................................................................................................................... 42

Write Burst Mode ....................................................................................................................................... 42

Bank/Row Activation ...................................................................................................................................... 43

READ Operation ............................................................................................................................................. 44

WRITE Operation ........................................................................................................................................... 53

Burst Read/Single Write .............................................................................................................................. 60

PRECHARGE Operation .................................................................................................................................. 61

Auto Precharge ........................................................................................................................................... 61

AUTO REFRESH Operation ............................................................................................................................. 73

SELF REFRESH Operation ............................................................................................................................... 75

Power-Down .................................................................................................................................................. 77

Clock Suspend ............................................................................................................................................... 78

PDF: 09005aef811ce1fe

64mb_x32_sdram.pdf - Rev. T 04/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

64Mb: x32 SDRAM

Features

List of Figures

Figure 1: 2 Meg x 32 Functional Block Diagram ................................................................................................. 8

Figure 2: 86-Pin TSOP (Top View) .................................................................................................................... 9

Figure 3: 90-Ball VFBGA (Top View) ............................................................................................................... 10

Figure 4: 86-Pin Plastic TSOP II (400 mil) – Package Codes TG/P ...................................................................... 12

Figure 5: 90-Ball VFBGA (8mm x 13mm) – Package Codes B5 ........................................................................... 13

Figure 6: Example: Temperature Test Point Location, 86-Pin TSOP (Top View) ................................................. 15

Figure 7: Example: Temperature Test Point Location, 90-Ball FBGA (Top View) ................................................ 16

Figure 8: ACTIVE Command .......................................................................................................................... 26

Figure 9: READ Command ............................................................................................................................. 27

Figure 10: WRITE Command ......................................................................................................................... 28

Figure 11: PRECHARGE Command ................................................................................................................ 29

Figure 12: Initialize and Load Mode Register .................................................................................................. 37

Figure 13: Mode Register Definition ............................................................................................................... 39

Figure 14: CAS Latency .................................................................................................................................. 42

Figure 15: Example: Meeting

RCD (MIN) When 2 <

RCD (MIN)/

CK < 3 .......................................................... 43

Figure 16: Consecutive READ Bursts .............................................................................................................. 45

Figure 17: Random READ Accesses ................................................................................................................ 46

Figure 18: READ-to-WRITE ............................................................................................................................ 47

Figure 19: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 48

Figure 20: READ-to-PRECHARGE .................................................................................................................. 48

Figure 21: Terminating a READ Burst ............................................................................................................. 49

Figure 22: Alternating Bank Read Accesses ..................................................................................................... 50

Figure 23: READ Continuous Page Burst ......................................................................................................... 51

Figure 24: READ – DQM Operation ................................................................................................................ 52

Figure 25: WRITE Burst ................................................................................................................................. 53

Figure 26: WRITE-to-WRITE .......................................................................................................................... 54

Figure 27: Random WRITE Cycles .................................................................................................................. 55

Figure 28: WRITE-to-READ ............................................................................................................................ 55

Figure 29: WRITE-to-PRECHARGE ................................................................................................................. 56

Figure 30: Terminating a WRITE Burst ............................................................................................................ 57

Figure 31: Alternating Bank Write Accesses ..................................................................................................... 58

Figure 32: WRITE – Continuous Page Burst ..................................................................................................... 59

Figure 33: WRITE – DQM Operation ............................................................................................................... 60

Figure 34: READ With Auto Precharge Interrupted by a READ ......................................................................... 62

Figure 35: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 63

Figure 36: READ With Auto Precharge ............................................................................................................ 64

Figure 37: READ Without Auto Precharge ....................................................................................................... 65

Figure 38: Single READ With Auto Precharge .................................................................................................. 66

Figure 39: Single READ Without Auto Precharge ............................................................................................. 67

Figure 40: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 68

Figure 41: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 68

Figure 42: WRITE With Auto Precharge ........................................................................................................... 69

Figure 43: WRITE Without Auto Precharge ..................................................................................................... 70

Figure 44: Single WRITE With Auto Precharge ................................................................................................. 71

Figure 45: Single WRITE Without Auto Precharge ............................................................................................ 72

Figure 46: Auto Refresh Mode ........................................................................................................................ 74

Figure 47: Self Refresh Mode .......................................................................................................................... 76

Figure 48: Power-Down Mode ........................................................................................................................ 77

Figure 49: Clock Suspend During WRITE Burst ............................................................................................... 78

Figure 50: Clock Suspend During READ Burst ................................................................................................. 79

PDF: 09005aef811ce1fe

64mb_x32_sdram.pdf - Rev. T 04/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

64Mb: x32 SDRAM

Features

Figure 51: Clock Suspend Mode ..................................................................................................................... 80

PDF: 09005aef811ce1fe

64mb_x32_sdram.pdf - Rev. T 04/13 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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