Obsolescence Notice
This product is obsolete.
This information is available for your
convenience only.
For more information on
Zarlink’s obsolete products and
replacement product lists, please visit
http://products.zarlink.com/obsolete_products/
P R E L I M I N A R Y
I N F O R M A T I O N
Distinctive Characteristics
t
Highly integrated central switch controller
t
State of the art 0.35 micron 3.3 Volt CMOS
process
t
256-PIN PQFP package
t
Operating frequency
◊
◊
◊
◊
◊
◊
-40
-50
-66
40 MHz maximum
50 MHz maximum
66 MHz maximum
SC220 – XpressFlow Engine
XpressFlow 2020 Ethernet Routing Switch Chipset
CAM
(Optional)
ADDRESS
MAPPING
TABLE
16
SC220
t
16-bit external CAM interface
Supports ½ to 16k MAC addresses
k
CONTROL
BUFFER
MEMORY
XpressFlow
32
t
32-bit Control Buffer Memory interface
Supports 128k to 1M bytes
Utilize high performance 32-bit Syn-
chronous Burst SRAM
ENGINE
t
Hardware assisted Buffer and Queue Man-
agement to minimize CPU overhead
t
32-bit Management Bus I/O interface
◊
◊
◊
Allows host to access CAM and Control
Buffer Memory
Supports Big and Little Endian CPUs
Direct interface with various different
standard microprocessors including
386, 486 families and Motorola MPC se-
ries embedded processors
Switching bandwidth
32
XpressFlow BUS
32
XpressFlow BUS
t
32-bit
XpressFlow Bus
Interface
◊
−1.28
Gbps @ 40 MHz system clock
−1.60
Gbps @ 50 MHz system clock
−2.10
Gbps @ 66.67 MHz system clock
◊
◊
◊
Supports up to 8 Multi-port Network Ac-
cess Controllers
XpressFlow
Bus access arbitration
XpressFlow
Bus data transfer load
regulation
Addresses resolved by SC220
Supports either CAM based or SRAM
based Switching data base
SC220 - XpressFlow Engine
General Description
The
XpressFlow
Engine contains the switching data base in-
terface and buffer management logic in order to do the switching
decision making for unicast, multicast, and broadcast frames.
Hardware assisted queue manager is incorporated to facilitate
buffer management. It also provides a generic Management Bus
interface to allow external processor to do initialization, learning,
VLAN, and RMON support, etc. In addition, a
XpressFlow Bus
interface block is responsible for communicating with the Network
Access Controllers through the
XpressFlow
message passing
protocol.
t
Full IP Switching
◊
◊
t
MAC Address Mapping Table
Related Components:
t
EA218E
– 8-port 10Mbps Ethernet Access Controller
t
EA218
– 6-port 10 + 2-port 10/100 Ethernet Access Controller
t
EA234
– 4-port 10/100 Fast Ethernet
© 1998
Vertex Networks, Inc.
1999
1
Rev. 4.5 – February
P
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XpressFlow-2020 Series –
Ethernet Switch Chipset
Characteristics Continue
t
Built-in address to port resolution
◊
◊
◊
Embedded 32-bit HISC™ (High density
Instruction Set Core) Processor
Optimized architecture for switch appli-
cations
Loadable firmware for easy upgrade
CAM
ADDRESS
MAPPING
TABLE
SC220
XpressFlow Engine
SC220
XpressFlow
Engine
HISC Core
32
32
t
Supports unicast, multicast, and broadcast
frames
t
Address Filtering
◊
Destination & Source MAC address
matching & filtering
Up to 62 groups
Level 1 and 2 mapping
VLAN ID tagging & stripping
Auto padding if necessary after stripping
16
CAM
Interface
16
16
SRAM
CONTROL
BUFFER
MEMORY
HISC
I/O
Registers
Mngmt
Bus
Interface
32
32
32
Control
Buffer
Memory
Interface
32
32
t
VLAN classification & verification
◊
◊
◊
◊
32
32
32
32
XpressFlow Bus
Interafce
32
Automatic
Buffer
Manager
XpressFlow BUS
t
Supports Store-&-Forward Frame Forward-
ing Mode
t
Collects statistics for RMON
Block Diagram –
SC220 XpressFlow Engine
Typical Application
:
◊
A 16-port Ethernet Switch with 4-Fast Ethernet
Address
Mapping
Table
RS232 Local
Control Console
Buffer
RAM
SC220
XpressFlow
Engine
Flash
ROM
Switch
Manager
CPU
DRAM
Management Bus
XpressFlow Bus
Buffer
RAM
EA208E
8-Port
Ethernet
Access
Controller
Buffer
RAM
EA208E
8-Port
Ethernet
Access
Controller
Buffer
RAM
EA234
4-Port
Ethernet
Access
Controller
8 Ethernet ports
8 Ethernet ports
Four 100M
Fast Ethernet ports
System Block Diagram --
16-Port Ethernet Switch with 4 Fast Ethernet Up-Links
© 1998
Vertex Networks, Inc.
1999
2
Rev. 4.5 – February
MANAGEMENT-BUS
P
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F
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XpressFlow-2020 Series –
Ethernet Switch Chipset
SC220
XpressFlow Engine
1. PIN ASSIGNMENT
1.1
Logic Symbol
SC220
L_A[18:2]
L_BWE[3:0]#
L_WE[3:0]#
L_OE[3:0]#
L_ADSC#
L_CLK
P_D[31:0]
P_A[11:1]
P_CS#
P_ADS#
P_RWC
P_RDY#
P_BS16#
P_INT
P_RSTIN#
P_RSTOUT
P_CLK
4
4
4
Control Buffer
Memory Interface
L_D[31:0]
Test Pin
T_MODE
C_D[15:0]
C_CE#
C_WE#
C_CM#
C_EC#
C_MF#
C_FF#
S_D[31:0]
S_MSGEN#
S_EOF#
S_IRDY
S_TABT#
S_OVLD#
8
8
Management Bus Interface
XpressFlow
Bus Interface
CAM Interface
S_HPREQ#
S_REQ[8:1]#
S_GNT[8:1]#
S_CLK
Note:
The SC220 is pin compatible to the SC201 with only one exception:
The RSTOUT pin of SC201 is defined as a synchronous RESET output pin which follows the RSTIN input and re-synchronous with
P_CLK for meeting the 80386 timing requirement.
The RSTOUT pin for SC220 has a totally different function. It is no longer related with the RSTIN input. The RSTOUT is a watch-
dog output from SC220 to keep track of the active state of the host processor. Host processor needs to access the Keep
Alive register periodically to prevent the setting of the RSTOUT output. The RSTOUT output can be use as Reset input to
the host processor.
© 1998
Vertex Networks, Inc.
1999
3
Rev. 4.5 – February
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XpressFlow-2020 Series –
Ethernet Switch Chipset
1.2
Pin Assignment
(Preliminary)
Note:
#
Input
I-ST
Output
Out-OD
I/O-TS
I/O-OD
5VT
Active low signal
Input signal
Input signal with Schmitt-Trigger
Output signal (Tri-State driver)
Output signal with Open-Drain driver
Input & Output signal with Tri-State driver
Input & Output signal with Open-Drain driver
Input with 5V Tolerance
Symbol
Type
SC220
XpressFlow Engine
Pin No(s).
Name & Functions
XpressFlow Bus Interface
122,121,119,118, 116 S_D[31:27] /
P_C[0:4]
114,113,111,109,108,
106,105,104,103,101,
100,98,97,96,95,93,92,
90,89,88,87,85,84,82,
80,79,77
71
69
72
70
123
140,138,135,133,131,
129,126,124
141,139,137,134,132,
130,128,125
73
75
S_D[26:0]
CMOS I/O-TS
XpressFlow
Bus – Data Bit [31:28]
or
Processor Interface Configuration Bit
[0:4]
CMOS I/O-TS
XpressFlow
Bus – Data Bit [27:0]
S_MSGEN#
S_EOF#
S_IRDY
S_TABT#
S_HPREQ#
S_REQ[8:1]#
S_GNT[8:1]#
S_OVLD#
S_CLK
CMOS I/O-TS
CMOS I/O-TS
CMOS I/O-TS
CMOS I/O-OD
CMOS I/O-OD
CMOS Input **
XpressFlow
Bus – Message Envelope
XpressFlow
Bus – End of Frame
XpressFlow
Bus – Initiator Ready
XpressFlow
Bus – Target Abort
XpressFlow
Bus – High Priority Request
XpressFlow
Bus – Bus Request [8:1]
CMOS Output
XpressFlow
Bus – Bus Grant [8:1]
CMOS Output
XpressFlow
Bus – Bus Overload
CMOS Input
XpressFlow
Bus – Clock
© 1998
Vertex Networks, Inc.
1999
4
Rev. 4.5 – February
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