2. Serial data is clocked in on the L to H transition of the CLK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flow through the latch.
4. D
OUT
is high when data in the shift register 7 is high.
5. Shift register clocking has no effect on the switch states if LE is high.
6. The CLR clear input overrides all other inputs.
5
HV2203
Low Charge Injection, 8-Channel
High Voltage Analog Switch
Features
►
►
►
►
►
►
►
►
►
►
►
HVCMOS technology for high performance
3.3V or 5.0V CMOS input logic level
20MHz data shift clock frequency
Very low quiescent power dissipation - 10µA
Low parasitic capacitance
DC to 10MHz analog signal frequency
-60dB typical off-isolation at 5MHz
CMOS logic circuitry for low power
Excellent noise immunity
Cascadable serial data register with latches
Flexible operating supply voltages
General Description
The Supertex HV2203 is a low charge injection 8-channel high
voltage analog switch integrated circuit (IC) intended for use in
applications requiring high voltage switching controlled by low
voltage signals, such as medical ultrasound imaging, piezoelectric
transducer driver, and printers.
Data is input into an 8-bit shift register that can then be retained
in an 8-bit latch. To reduce any possible clock feed-through noise,
the latch enable bar should be left high until all bits are clocked in.
Data is clocked in during the rising edge of the clock.
Using HVCMOS technology, this device combines high voltage
bilateral DMOS switches and low power CMOS logic to provide
efficient control of high voltage analog signals.
The device is suitable for various combinations of high voltage
supplies, e.g., V
PP
/V
NN
: +40V/-120V, +80V/-80V, and +120V/-40V.
Applications
►
►
►
►
►
Medical ultrasound imaging
NDT metal flaw detection
Piezoelectric transducer drivers
Inkjet printer heads
Optical MEMS modules
Block Diagram
LEVEL
OUTPUT
SHIFTERS &
LATCHES
SWITCHES
CHARGE CONTROL
D
LE
CLR
SW0
CLK
D
LE
CLR
SW1
D
IN
8-BIT
SHIFT
REGISTER
D
LE
CLR
SW2
D
OUT
D
LE
CLR
SW6
D
LE
CLR
SW7
VDD GND
LE
CLR
VNN VPP
HV2203
Ordering Information
Device
HV2203
Package Options
37
Pin Configurations
36
25
24
48-Lead LQFP
HV2203FG-G
28-Lead PLCC
HV2203PJ-G
-G indicates package is RoHS compliant (‘Green’)
48
1
12
13
48-Lead LQFP (FG)
Absolute Maximum Ratings
Parameter
V
DD
logic supply
V
PP
-V
NN
differential supply
V
PP
positive supply
V
NN
negative supply
Logic input voltage
Analog signal range
Peak analog signal current/channel
Storage temperature
Thermal resistance (θ
ja
):
48-Lead LQFP (FG)
Value
-0.5V to +6.5V
170V
-0.5V to V
NN
+170V
+0.5V to -170V
-0.5V to V
DD
+0.3V
V
NN
to V
PP
1.0A
-65°C to 150°C
61
O
C/W
28-Lead PLCC (PJ)
Product Marking
Top Marking
YYWW
HV2203FG
LLLLLLLLL
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. Continuous operation of the device at
the absolute rating level may affect device reliability. All voltages are referenced to device ground.
Bottom Marking
CCCCCCCC
AAA
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Operating Conditions
Sym
V
DD
V
PP
V
NN
V
IH
V
IL
V
SIG
T
A
Parameter
Logic power supply voltage
Positive high voltage supply
Negative high voltage supply
High level input voltage
Low-level input voltage
Analog signal voltage peak-to-peak
Operating free air temperature
Value
3.0V to 5.5V
40V to V
NN
+160V
-40V to -120V
0.9V
DD
to V
DD
0V to 0.1V
DD
V
NN
+10V to V
PP
-10V
0
O
C to 70
O
C
48-Lead LQFP (FG)
Top Marking
YY W W
HV2203PJ
LLLLLLLLLL
Bottom Marking
CCCCCCCCCCC
AAA
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Notes:
1. Power up/down sequence is arbitrary except GND must be powered-up first and powered-
2. Serial data is clocked in on the L to H transition of the CLK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flow through the latch.
4. D
OUT
is high when data in the shift register 7 is high.
5. Shift register clocking has no effect on the switch states if LE is high.
6. The CLR clear input overrides all other inputs.
I use ACLK/256and set the interrupt frequency selection bits IP2 and IP1, so the interrupt frequency isACLK/256=128128/128=1, which means one interrupt per second?Why is there such a large error of 15...
I am going to design a pocket toolbox for engineers based on [b]MicroPython[/b]. The main purpose is to be a practical tool, not just a development board or a learning board. [b]Main purpose[/b] [list...
Has anyone used the spi mode of the USI of the 2 series? How come there is only one send and receive register? When is it sent and when is it received?...
Abstract:
With the increasing complexity of smart vehicle electrical and electronic architectures, the full lifecycle management of vehicle electronic control components faces multiple challe...[Details]
We are entering a new era where people are increasingly affordably equipped with more electronic gadgets. Electronics have become essential to our lives. For example, the average consumer now owns ...[Details]
For healthcare professionals, accurate diagnosis and treatment are crucial for a clear picture of a person's health. However, healthcare professionals often rely on tests at medical facilities, cli...[Details]
On August 22nd, Lantu Motors unveiled a new technology called "Lanhai Intelligent Hybrid" during a live broadcast of CCTV News' "Top Laboratory." The name sounds like another new term, but a closer...[Details]
Gross profit margin jumped from 13.6% in the first half of last year to 25.9%, almost doubling year-on-year.
On August 21, RoboSense released its interim performance report, in which the...[Details]
On August 22, South Korean media Nate reported on the 20th local time that Samsung Electronics is introducing Hyper Cell technology into its most advanced 2nm process technology, striving to improv...[Details]
SMT placement machines are important equipment in surface mount technology (Surface Mount Technology). Their performance has a decisive impact on the quality and efficiency of electronic manufactur...[Details]
Industrial computers with GPUs leverage powerful parallel processing to build deep learning models to analyze and respond to optical inputs. The systems develop an understanding of visual data to i...[Details]
PowiGaN achieves 95% efficiency at both light and full loads, meeting critical operational and safety requirements.
DARWIN, Australia and SAN JOSE, Calif.,
August 22, 2025 – Powe...[Details]
Reflow soldering, as an electronics assembly process, has become a vital component of the electronics manufacturing industry. Choosing reflow soldering equipment is crucial for improving production...[Details]
The screen is the first thing you notice when evaluating a phone's quality. Its quality directly impacts both visual and operational performance. However, understanding mobile phone screens r...[Details]
With the continuous development of ultrasonic technology, ultrasound has been widely used in fields such as inspection, cleaning, welding, and medical treatment, and has even found its way into tex...[Details]
This article uses the Allwinner T507 quad-core automotive-grade processor as the development board. This article explains how to configure Ethernet for the T507 development board. Other boards may ...[Details]
Recently, I received a request to use OK1028A-C to output PWM square wave. However, I found that there was no relevant instructions on the OK1028 platform, so I started writing this article.
A...[Details]
On August 19, Huawei's Executive Director and Chairman of the Device BG, Richard Yu, shared a Weibo post about a conversation he had with a Zunjie S800 owner. The owner had driven over 5,000 kilome...[Details]
Microcontroller MCU
京公网安备 11010802033920号
EEWORLD
