HV2203PJ-G datasheet, PDF - EEWORLD Datasheet

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HV2203PJ-G: DescriptionSingle-Ended Multiplexer, 8 Func, 1 Channel, CMOS, PQCC28, 0.453 X 0.453 INCH, 0.180 INCH HEIGHT, 0.050 INCH PITCH,GREEN, PLASTIC, MS-018AB, LCC-28; CategoryAnalog mixed-signal IC The signal circuit; File Size833KB，9 Pages; ManufacturerSupertex; Environmental Compliance

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HV2203PJ-G Overview

Single-Ended Multiplexer, 8 Func, 1 Channel, CMOS, PQCC28, 0.453 X 0.453 INCH, 0.180 INCH HEIGHT, 0.050 INCH PITCH,GREEN, PLASTIC, MS-018AB, LCC-28

HV2203PJ-G Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Supertex
Parts packaging code	LCC
package instruction	QCCJ,
Contacts	28
Reach Compliance Code	compliant
Other features	IT ALSO REQUIRES VPP (40V TO VNN +160V) AND VNN (-40V TO -120V) SUPPLY
Analog Integrated Circuits - Other Types	SINGLE-ENDED MULTIPLEXER
JESD-30 code	S-PQCC-J28
JESD-609 code	e3
length	11.5062 mm
Humidity sensitivity level	1
Number of channels	1
Number of functions	8
Number of terminals	28
Nominal off-state isolation	33 dB
On-state resistance matching specifications	5 Ω
Maximum on-state resistance (Ron)	60 Ω
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
Maximum disconnect time	5000 ns
Maximum connection time	5000 ns
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	11.5062 mm

HV2203PJ-G Preview

HV2203

Low Charge Injection, 8-Channel

High Voltage Analog Switch

Features

►

HVCMOS technology for high performance

3.3V or 5.0V CMOS input logic level

20MHz data shift clock frequency

Very low quiescent power dissipation - 10µA

Low parasitic capacitance

DC to 10MHz analog signal frequency

-60dB typical off-isolation at 5MHz

CMOS logic circuitry for low power

Excellent noise immunity

Cascadable serial data register with latches

Flexible operating supply voltages

General Description

The Supertex HV2203 is a low charge injection 8-channel high

voltage analog switch integrated circuit (IC) intended for use in

applications requiring high voltage switching controlled by low

voltage signals, such as medical ultrasound imaging, piezoelectric

transducer driver, and printers.

Data is input into an 8-bit shift register that can then be retained

in an 8-bit latch. To reduce any possible clock feed-through noise,

the latch enable bar should be left high until all bits are clocked in.

Data is clocked in during the rising edge of the clock.

Using HVCMOS technology, this device combines high voltage

bilateral DMOS switches and low power CMOS logic to provide

efﬁcient control of high voltage analog signals.

The device is suitable for various combinations of high voltage

supplies, e.g., V

: +40V/-120V, +80V/-80V, and +120V/-40V.

Applications

►

Medical ultrasound imaging

NDT metal ﬂaw detection

Piezoelectric transducer drivers

Inkjet printer heads

Optical MEMS modules

Block Diagram

LEVEL

OUTPUT

SHIFTERS &

LATCHES

SWITCHES

CHARGE CONTROL

CLR

SW0

CLK

CLR

SW1

8-BIT

SHIFT

CLR

SW2

OUT

CLR

SW6

CLR

SW7

VDD GND

CLR

VNN VPP

HV2203

Ordering Information

Device

HV2203

Package Options

Pin Conﬁgurations

48-Lead LQFP

HV2203FG-G

28-Lead PLCC

HV2203PJ-G

-G indicates package is RoHS compliant (‘Green’)

48-Lead LQFP (FG)

Absolute Maximum Ratings

Parameter

logic supply

-V

differential supply

positive supply

negative supply

Logic input voltage

Analog signal range

Peak analog signal current/channel

Storage temperature

Thermal resistance (θ

48-Lead LQFP (FG)

Value

-0.5V to +6.5V

170V

-0.5V to V

+170V

+0.5V to -170V

-0.5V to V

+0.3V

to V

1.0A

-65°C to 150°C

C/W

28-Lead PLCC (PJ)

Product Marking

Top Marking

YYWW

HV2203FG

LLLLLLLLL

Absolute Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation under these conditions is not implied. Continuous operation of the device at

the absolute rating level may affect device reliability. All voltages are referenced to device ground.

Bottom Marking

CCCCCCCC

AAA

YY = Year Sealed

WW = Week Sealed

L = Lot Number

C = Country of Origin*

A = Assembler ID*

= “Green” Packaging

*May be part of top marking

Operating Conditions

Sym

SIG

Parameter

Logic power supply voltage

Positive high voltage supply

Negative high voltage supply

High level input voltage

Low-level input voltage

Analog signal voltage peak-to-peak

Operating free air temperature

Value

3.0V to 5.5V

40V to V

+160V

-40V to -120V

0.9V

to V

0V to 0.1V

+10V to V

-10V

C to 70

48-Lead LQFP (FG)

Top Marking

YY W W

HV2203PJ

LLLLLLLLLL

Bottom Marking

CCCCCCCCCCC

AAA

YY = Year Sealed

WW = Week Sealed

L = Lot Number

C = Country of Origin

A = Assembler ID*

= “Green” Packaging

*May be part of top marking

Notes:

1. Power up/down sequence is arbitrary except GND must be powered-up ﬁrst and powered-

down last.

2. V

SIG

must be V

≤ V

SIG

≤ V

or ﬂoating during power up/down transition.

3. Rise and fall times of power supplies V

, V

, and V

should not be less than 1.0msec.

28-Lead PLCC (PJ)

HV2203

DC Electrical Characteristics

(Over operating conditions unless otherwise speciﬁed )

Sym Parameter

Min

+25

Min

1.0

0.45

+70

Max

300

500

-50

1.5

4.0

Max

5.0

300

500

4.0

Typ

5.0

1.0

100

-10

1.0

1.2

0.70

Min

0.40

Max

300

500

4.0

Units Conditions

SIG

= 5.0mA

SIG

= 200mA

SIG

= 5.0mA

SIG

= 200mA

SIG

= 5.0mA

SIG

= 200mA

μA

kHz

= +40V

= -120V

= +80V

= -80V

= +120V

= -40V

ONS

Small signal switch

on-resistance

ΔR

ONS

ONL

SOL

PPQ

NNQ

PPQ

NNQ

Small signal switch

on-resistance matching

Large signal switch

on-resistance

Switch off leakage per switch

DC offset switch off

DC offset switch on

Quiescent V

supply current

Quiescent V

supply current

Quiescent V

supply current

Quiescent V

supply current

Switch output peak current

Output switching

frequency

SIG

= 5.0mA, V

= +80V,

= -80V

SIG

= V

-10V, I

SIG

= 0.5A

SIG

= V

-10V, V

+10V

100kΩ load

All switches off

All switches on, I

= 5.0mA

All switches on, I

= 5.0mA

SIG

duty cycle < 0.1%, 1.0μs

Duty cycle = 50%

= +40V

= -120V

All output

switches are

turning on

and off at

50kHz with

no load

All output

switches are

turning on

and off at

50kHz with

no load

Average V

supply current

= +80V

= -80V

= +120V

= -40V

= +40V

= -120V

Average V

supply current

= +80V

= -80V

= +120V

= -40V

DDQ

SOR

SINK

Average V

supply current

Quiescent V

supply current

Data out source current

Data out sink current

Logic input capacitance

0.45

μA

CLK

= 5.0MHz, V

= 5.0V

All logic inputs are static

OUT

= V

-0.7V

OUT

= 0.7V

---

HV2203

AC Electrical Characteristics

(Over recommended operating conditions: V

= 5.0V, t

= t

≤5ns, 50% duty cycle, C

LOAD

= 20pF, unless otherwise speciﬁed)

Sym

WLE

Parameter

Set up time before LE rises

Time width of LE

Min

+25

Min

2.0

+70

Max

100

8.0

5.0

300

Max

100

8.0

5.0

300

Typ

7.0

Min

7.0

2.0

-30

-58

-60

Max

100

8.0

MHz

5.0

300

V/ns

μs

Conditions

---

= 3.0V

= 5.0V

= 3.0V

= 5.0V

---

= 3.0V

= 5.0V

= 3.0 or 5.0V

= 3.0V

= 5.0V

---

SIG

= V

-10V, R

LOAD

= 10kΩ

SIG

= V

-10V, R

LOAD

= 10kΩ

= +40V, V

= -120V

= +80V, V

= -80V

= +120V, V

= -40V

f = 5.0MHz, 1.0kΩ/15pF load

f = 5.0MHz, 50Ω load

300ns pulse width,

2.0% duty cycle

0V, f = 1.0MHz

= +40V, V

= -120V,

LOAD

= 50Ω

= +80V, V

= -80V,

LOAD

= 50Ω

= +120V, V

= -40V,

LOAD

= 50Ω

= +40V, V

= -120V,

SIG

= 0V

= +80V, V

= -80V,

SIG

= 0V

= +120V, V

= -40V,

SIG

= 0V

WCL

CLK

, t

OFF

dv/dt

Clock delay time to data out

Time width of CLR

Set up time data to clock

7.0

Hold time data from clock

Clock frequency

Clock rise and fall times

Turn on time

Turn off time

Maximum V

SIG

slew rate

2.0

-30

-58

-60

-33

-70

6.5

21.7

270

220

152

Off isolation

Switch crosstalk

Output switch isolation diode

current

-30

-58

-60

SG(OFF)

Off capacitance SW to GND

SG(ON)

SPK

-V

SPK

-V

SPK

-V

SPK

Output voltage spike

On capacitance SW to GND

Charge injection

HV2203

Truth Table

CLR

Hold Previous State

All Switches Off

SW0

Off

SW1

SW2

SW3

SW4

SW5

SW6

SW7

Notes:

1. The eight switches operate independently.

2. Serial data is clocked in on the L to H transition of the CLK.

3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data ﬂow through the latch.

4. D

OUT

is high when data in the shift register 7 is high.

5. Shift register clocking has no effect on the switch states if LE is high.

6. The CLR clear input overrides all other inputs.

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