14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
1.8 V Dual Analog-to-Digital Converter
Data Sheet
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR
74.3 dBFS at 9.7 MHz input
71.5 dBFS at 200 MHz input
SFDR
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input
Low power
33 mW per channel at 20 MSPS
73 mW per channel at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.45 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data
alignment
AVDD
GND
SDIO SCLK CSB
AD9251
FUNCTIONAL BLOCK DIAGRAM
SPI
CMOS
OUTPUT BUFFER
ORA
D13A
D0A
DCOA
VIN+A
ADC
VIN–A
PROGRAMMING DATA
VREF
SENSE
VCM
RBIAS
VIN–B
ADC
VIN+B
REF
SELECT
MUX OPTION
AD9251
DRVDD
CMOS
OUTPUT BUFFER
ORB
D13B
D0B
DCOB
DIVIDE
1 TO 8
DUTY CYCLE
STABILIZER
MODE
CONTROLS
07938-001
CLK+ CLK–
SYNC
DCS
PDWN DFS OEB
Figure 1.
PRODUCT HIGHLIGHTS
1.
The AD9251 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
The patented sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
A standard serial port interface supports various product
features and functions, such as data output formatting,
internal clock divider, power-down, DCO/DATA timing
and offset adjustments, and voltage reference modes.
The AD9251 is packaged in a 64-lead RoHS compliant
LFCSP that is pin compatible with the
AD9268
16-bit
ADC, the
AD9258
14-bit ADC, the
AD9231
12-bit ADC,
and the
AD9204
10-bit ADC, enabling a simple migration
path between 10-bit and 16-bit converters sampling from
20 MSPS to 125 MSPS.
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Battery-powered instruments
Hand held scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
2.
3.
4.
Rev. B
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Trademarks and registered trademarks are the property of their respective owners.
AD9251* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
REFERENCE MATERIALS
Product Selection Guide
•
RF Source Booklet
Technical Articles
•
Designing 1-ppm DAC Accuracy into Instrumentation
Applications - Part 1
•
Designing 1-ppm DAC Accuracy into Instrumentation
Applications - Part 2
•
Improve The Design Of Your Passive Wideband ADC
Front-End Network
•
MS-2210: Designing Power Supplies for High Speed ADC
EVALUATION KITS
•
AD9251 Evaluation Board
DOCUMENTATION
Application Notes
•
AN-1142: Techniques for High Speed ADC PCB Layout
•
AN-742: Frequency Domain Response of Switched-
Capacitor ADCs
•
AN-807: Multicarrier WCDMA Feasibility
•
AN-808: Multicarrier CDMA2000 Feasibility
•
AN-812: MicroController-Based Serial Port Interface (SPI)
Boot Circuit
•
AN-827: A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs
•
AN-878: High Speed ADC SPI Control Software
•
AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
•
AN-935: Designing an ADC Transformer-Coupled Front
End
Data Sheet
•
AD9251: 14-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8
V Dual Analog-to-Digital Converter Data Sheet
User Guides
•
UG-003: Evaluating the AD9650/AD9268/AD9258/
AD9251/AD9231/AD9204 Analog-to-Digital Converters
DESIGN RESOURCES
•
AD9251 Material Declaration
•
PCN-PDN Information
•
Quality And Reliability
•
Symbols and Footprints
DISCUSSIONS
View all AD9251 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
TOOLS AND SIMULATIONS
•
Visual Analog
•
AD9251 IBIS Models
•
AD9204/AD9231/AD9251 S-Parameter Data
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
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AD9251
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications.......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Timing Specifications .................................................................. 8
Absolute Maximum Ratings .......................................................... 10
Thermal Characteristics ............................................................ 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 13
AD9251-80 .................................................................................. 13
AD9251-65 .................................................................................. 15
AD9251-40 .................................................................................. 16
AD9251-20 .................................................................................. 17
Equivalent Circuits ......................................................................... 18
Theory of Operation ...................................................................... 20
ADC Architecture ...................................................................... 20
Analog Input Considerations.................................................... 20
Data Sheet
Voltage Reference ....................................................................... 23
Clock Input Considerations ...................................................... 24
Channel/Chip Synchronization ................................................ 26
Power Dissipation and Standby Mode .................................... 26
Digital Outputs ........................................................................... 27
Timing.......................................................................................... 27
Built-In Self-Test (BIST) and Output Test .................................. 28
Built-In Self-Test (BIST) ............................................................ 28
Output Test Modes ..................................................................... 28
Serial Port Interface (SPI) .............................................................. 29
Configuration Using the SPI ..................................................... 29
Hardware Interface ..................................................................... 30
Configuration Without the SPI ................................................ 30
SPI Accessible Features .............................................................. 30
Memory Map .................................................................................. 31
Reading the Memory Map Register Table............................... 31
Open Locations .......................................................................... 31
Default Values ............................................................................. 31
Memory Map Register Table ..................................................... 32
Memory Map Register Descriptions ........................................ 34
Applications Information .............................................................. 35
Design Guidelines ...................................................................... 35
Outline Dimensions ....................................................................... 36
Ordering Guide .......................................................................... 36
REVISION HISTORY
9/2016—Rev. A to Rev. B
Changes to Figure 3 .......................................................................... 8
10/2009—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Change to Table 1 ............................................................................. 4
Moved Timing Diagrams................................................................. 8
Deleted Table 11; Renumbered Sequentially .............................. 22
Changes to Internal Reference Connection Section .................. 23
Moved Channel/Chip Synchronization Section......................... 26
Change to Table 15 ......................................................................... 30
Changes to Reading the Memory Map Register
Table Section ................................................................................... 31
Changes to Table 16 ....................................................................... 32
7/2009—Revision 0: Initial Version
Rev. B | Page 2 of 36
Data Sheet
GENERAL DESCRIPTION
The AD9251 is a monolithic, dual-channel, 1.8 V supply,
14-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital
converter (ADC). It features a high performance sample-and-
hold circuit and on-chip voltage reference.
The product uses multistage differential pipeline architecture
with output error correction logic to provide 14-bit accuracy at
80 MSPS data rates and to guarantee no missing codes over the
full operating temperature range.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom
user-defined test patterns entered via the serial port interface (SPI).
AD9251
A differential clock input controls all internal conversion cycles.
An optional duty cycle stabilizer (DCS) compensates for wide
variations in the clock duty cycle while maintaining excellent
overall ADC performance.
The digital output data is presented in offset binary, gray code,
or twos complement format. A data output clock (DCO) is
provided for each ADC channel to ensure proper latch timing
with receiving logic. Both 1.8 V and 3.3 V CMOS levels are
supported and output data can be multiplexed onto a single
output bus.
The AD9251 is available in a 64-lead RoHS Compliant LFCSP
and is specified over the industrial temperature range (−40°C
to +85°C).
Rev. B | Page 3 of 36
AD9251
SPECIFICATIONS
DC SPECIFICATIONS
Data Sheet
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS,
DCS disabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
1
Differential Nonlinearity (DNL)
2
Integral Nonlinearity (INL)
2
MATCHING CHARACTERISTICS
Offset Error
Gain Error
1
TEMPERATURE DRIFT
Offset Error
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Load Regulation Error at 1.0 mA
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance
3
Input Common-Mode Voltage
Input Common-Mode Range
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD
2
IDRVDD
2
(1.8 V)
IDRVDD
2
(3.3 V)
POWER CONSUMPTION
DC Input
Sine Wave Input (DRVDD = 1.8 V)
Sine Wave Input
2
(DRVDD = 3.3 V)
2
Temp
Full
Full
Full
Full
Full
25°C
Full
25°C
25°C
25°C
Full
Full
Full
25°C
Full
Full
Full
Full
Full
AD9251-20/AD9251-40
Min
Typ
Max
14
Guaranteed
±0.1
±0.70
−1.5
±0.60
±0.3
±1.75
±0.6
±0.0
±0.2
±2
0.981
0.993
2
0.98
2
6
0.9
0.5
7.5
1.3
1.005
±0.65
AD9251-65
Min
Typ
Max
14
Guaranteed
±0.1
±0.50
−1.5
±0.75
±0.45
±1.75
±0.6
±0.0
±0.2
±2
0.981
0.993
2
0.98
2
6
0.9
0.5
7.5
1.3
1.005
±0.65
AD9251-80
Min
Typ
Max
14
Guaranteed
±0.1
±0.70
−1.5
±0.70
±0.45
±2.50
±1.0
±0.0
±0.2
±2
0.981
0.993
2
0.98
2
6
0.9
0.5
7.5
1.3
1.005
±0.65
Unit
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
% FSR
% FSR
ppm/°C
V
mV
LSB rms
V p-p
pF
V
V
kΩ
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
1.7
1.7
1.8
1.9
3.6
39.4/52.8
1.7
1.7
1.8
1.9
3.6
72.9
1.7
1.7
1.8
1.9
3.6
85.5
V
V
mA
mA
mA
mW
mW
mW
mW
mW
36.5/49.5
3.4/5.6
6.3/10.6
66/89
71.8/99
86.5/124
37
2.2
69.0
8.4
16.0
125
139.0
176.7
37
2.2
80.5
10.3
19.5
145
163.4
209
37
2.2
77.0/105.5
146.5
173
Standby Power
4
Power-Down Power
1
2
Measured with 1.0 V external reference.
Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
4
Standby power is measured with a dc input and the CLK active.
Rev. B | Page 4 of 36
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