a
FEATURES
Two Matched ADCs on Single Chip
CMOS-Compatible I/O
Low-Power (400 mW) Dissipation
Single +5 V Supply
On-Chip Voltage Reference
Self-Biased for AC-Coupled Inputs
28-Lead SOIC and SSOP Packages
APPLICATIONS
Direct Broadcast Satellite (DBS) Receivers
QAM Demodulators
Wireless LANs
VSAT Receivers
Dual 6-Bit, 60 MSPS
Monolithic A/D Converter
AD9066
FUNCTIONAL BLOCK DIAGRAM
+V
S
AD9066
VT
INA
REF A
ENCODE
INB
REF B
VB
6-BIT
DAC
D0B-D5B
6-BIT
DAC
D0A-D5A
PRODUCT DESCRIPTION
PIN CONFIGURATIONS
ENCODE
1
+V
S 2
GND
3
GND
4
+V
S 5
INA
6
GND
7
+V
S
28
D5A (MSB)
27
D4A
26
D3A
25
D2A
24
D1A
The AD9066 is a dual 6-bit ADC that has been optimized for
low-cost in-phase and quadrature (I and Q) demodulators.
Primary applications include digital direct broadcast satellite
applications where broadband quadrature phase shift keying
(QPSK) modulation is used. In these receivers the recovered signal
is separated into I and Q vector components and digitized.
To reduce total system cost and power dissipation, the AD9066
provides an internal voltage reference and operates from a
single +5 volt power supply. Digital outputs are CMOS com-
patible and rated to 60 MSPS conversion rates. The digital
input (ENCODE) utilizes a CMOS input stage with a TTL
compatible (1.4 V) threshold.
The AD9066 is housed in a 28-lead SOIC and a 28-lead SSOP
package and is available in two temperature grades. The
AD9066JR is rated for operation over the 0°C to 70°C commer-
cial temperature range. The AD9066AR/ARS is rated for the
–40°C to +85°C industrial temperature range.
The internal voltage reference insures that the analog input is
biased to midscale with low offset when driven from an ac-
coupled source. In dc-coupled applications, the midscale voltage
reference can be used to control external biasing amplifiers to
minimize offsets due to variations in temperature or supply voltage.
AD9066
(JR/AR)
TOP VIEW
23
D0A (LSB)
22
GND
8
(Not to Scale)
21
+V
S
20
D5B (MSB)
19
D4B
18
D3B
17
D2B
16
D1B
15
D0B (LSB)
VT
9
REF A
10
INB
11
REF B
12
VB
13
NC
14
NC = NO CONNECT
+V
S 1
VT
2
REF A
3
INB
4
REF B
5
VB
6
NC
7
28
GND
27
INA
26
+V
S
25
GND
24
GND
AD9066
(ARS)
23
+V
S
TOP VIEW
22
ENCODE
(Not to Scale)
21
D5A (MSB)
(LSB) D0B
8
D1B
9
D2B
10
D3B
11
D4B
12
(MSB) D5B
13
+V
S 14
20
D4A
19
D3A
18
D2A
17
D1A
16
D0A (LSB)
15
GND
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
NC = NO CONNECT
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD9066–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(+V = +5 V, AIN = 15.5 MHz, Encode Rate = 60 MSPS, T
S
C
= T
A
)
Unit
mV
mV
V
LSBs
pF
kΩ
MHz
dB
LSBs
LSBs
Parameter
ANALOG INPUT
Full-Scale Input Range
Gain Matching (FS Range)
DC Input (Midscale)
1
Input Offset
1
Input Capacitance
Input Resistance (DC)
Input Bandwidth (3 dB)
Gain Flatness (to 15 MHz)
Integral Linearity
Differential Linearity
Monotonicity
SWITCHING PERFORMANCE
Max Conversion Rate
Output Delay (t
V
)
2
Output Delay (t
PD
)
2
Aperture Uncertainty (Jitter)
Aperture Time (t
A
)
DYNAMIC PERFORMANCE
3
Effective Number of Bits
SINAD
Harmonic Distortion (THD)
Crosstalk Rejection
ENCODE INPUT
Logic High Voltage
Logic Low Voltage
Input High Current
Input Low Current
Pulsewidth High
Pulsewidth Low
DIGITAL OUTPUTS
Output Coding
Logic High Voltage (I
OH
= 1 mA)
Logic Low Voltage (I
OL
= 1 mA)
POWER SUPPLY
+V
S
Supply Voltage
Power Supply Rejection Ratio
1
+V
S
Supply Current
Power Dissipation
4
Test
Level
VI
IV
V
VI
IV
VI
V
V
VI
VI
VI
VI
IV
IV
V
V
VI
VI
VI
IV
VI
VI
VI
VI
IV
IV
Temp
Full
Full
+25°C
Full
Full
Full
+25°C
+25°C
Full
Full
Full
Full
Full
Full
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9066JR
Min
Typ
475
500
+V
S
– 1.1
–1.0
25
10
45
100
0.25
Max
525
16
+1.0
15
55
AD9066AR/ARS
Min
Typ
Max
450
500
+V
S
– 1.1
–1.0
22
10
45
100
0.25
+1.0
15
57
530
16
–1.0
–0.5
Guaranteed
60
4
+1.0
+0.5
–1.0
–0.5
Guaranteed
60
4
+1.0
+0.5
11
10
1.0
5.3
34
40
40
2.0
0.8
500
500
7.0
7.0
Offset Binary
3.8
0.4
4.75
110
80
400
5.25
130
120
600
4.75
110
80
400
3.8
7.0
7.0
Offset Binary
5.7
36
50
50
5.2
33
40
40
2.0
10
1.0
5.7
36
50
50
12
MSPS
ns
ns
ps rms
ns
Bits
dB
dB
dBc
V
V
µA
µA
ns
ns
0.8
500
500
VI
VI
VI
IV
VI
VI
0.4
5.25
130
120
600
V
V
V
mV/V
mA
mW
NOTES
1
For ac coupled applications, the ADC is internally biased to insure that the midpoint transition of the ADC is within the limits specified with no signal applied. For
dc coupled applications, the dc value of the midpoint transition voltage will track the supply voltage within the limits shown for dc input (midscale) plus the dc offset.
Power Supply Rejection Ratio (PSRR) refers to the variation of the input signal range (gain) to supply voltage.
2
t
V
and t
PD
are measured from the 1.4 V level of the Clock and the 50% level between V
OH
and V
OL
. The ac load on all the digital outputs during test is 10 pF (max),
the dc load will not exceed
±
40
µA.
3
Effective number of bits (ENOB) and THD are measured using a FFT with a pure sine wave analog input @ 15.5 MHz, 1 dB below full scale. ENOB is calculated by
ENOB = (SNR – 1.76 dB)/6.02; THD is measured from full scale to the sum of the second through seventh harmonic of the input.
4
Typical thermal impedance for the “R” style (SOIC) 28-lead package is:
θ
JC
= 4°C/W,
θ
CA
= 41°C/W,
θ
JA
= 45°C/W, and the “RS” style (SSOP) 28-lead package is:
θ
JC
= 26.97°C/W,
θ
CA
= 51.61°C/W,
θ
JA
= 78.58°C/W.
Specifications subject to change without notice.
–2–
REV. A
AD9066
ABSOLUTE MAXIMUM RATINGS
PIN DESCRIPTIONS
Pin
ENCODE
+V
S
INA, INB
VT
REF A, REF B
VB
D0–D5 Current OUT
Min
–0.5
–0.5
2.5
–0.5
0.0
Max
+V
S
7.0
+V
S
+V
S
+V
S
+V
S
20
Unit
V
V
V
V
V
V
mA
AR:JR ARS
Pin
Pin
No.
No. Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
ENCODE
+V
S
GND
GND
+V
S
INA
GND
+V
S
VT
REF A
INB
REF B
VB
NC
D0B (LSB)
Function
TTL Compatible CMOS Clock,
Samples on Rising Edge.
+5 V Supply for Digital Input.
Ground.
Ground.
+5 V Supply (Analog).
Channel A Analog Input.
Ground.
+5 V Supply (Analog).
Top of Voltage Reference, Bypass
to GND.
Mid Reference to ADC A, Bypass
to GND.
Channel B Analog Input.
Mid Reference to ADC B, Bypass
to GND.
Bottom of Reference Ladder, By-
pass to GND.
No Connect.
Digital Outputs Channel B,
CMOS Compatible.
EXPLANATION OF TEST LEVELS
Test Level
I
II
III
IV
V
VI
Description
100% Production Tested
100% Production Tested at +25°C, and
Sample Tested at Specified Temperatures
Sample Tested Only
Parameter Is Guaranteed by Design
Parameter Is Typical Value Only
100% Tested at +25°C
DIE LAYOUT AND MECHANICAL INFORMATION
Die Dimensions . . . . . . . . . . . . . . . . . 132
×
68
×
21 (± 1) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
×
4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5,810
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . Silicon Nitride
Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Silver Filled
Bond Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
ORDERING GUIDE
Model
AD9066AR
AD9066JR
AD9066ARS
Temperature Range
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
Package Option*
R-28
R-28
RS-28
*R = “SO” Small Outline Package; RS = SSOP.
D1B
D2B
D3B
D4B
D5B (MSB)
+V
S
+5 V Supply for Digital Outputs.
GND
Ground.
D0A (LSB) Digital Outputs Channel A,
CMOS Compatible.
D1A
D2A
D3A
D4A
D5A (MSB)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9066 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
AD9066
5.8
ENCODE = 60MSPS
5.7
Gain Variation
5.6
ENOB – Bits
The full-scale input range is established by the current through
the two matched resistor ladders (620 ohms each nominal). There-
fore the gain of the ADC may be modified by forcing different
voltages across the top and bottom voltage taps (VT and VB).
The easiest way to increase the input range will be to force VB
to a lower voltage. Using an external amplifier, the voltage at VB
may be forced as low as 3.0 V (3.58 nominal). Using the pre-
viously described relationship for full scale and the internal
resistor ladder values, 3.0 V at VB will result in a nominal full-
scale input range of 705 mV.
A larger input range can be established by taking the VT voltage
all the way to the supply voltage level while pulling VB to 3.0 V.
This would force a 2 V potential across the ladder and create a
full-scale input range of 1.6 V.
Greater flexibility and improved power supply rejection can be
achieved by forcing external voltage references at both the top
and bottom of the resistor ladder.
111111
5.5
5.4
5.3
5.2
1
10
MHz
100
Figure 1. ENOB vs. Analog Input Frequency
5.8
ANALOG INPUT = 10.1MHz
5.7
5.6
ENOB – Bits
2
n
–2 = 62
100000
5.5
011111
5.4
5.3
000001
000000
5.2
10
MHz
100
–FULL-SCALE
MIDSCALE
+FULL-SCALE
Figure 2. ENOB vs. Encode Rate
USING THE AD9066
Analog Input and Voltage References
+V
S
= 5V
400
VT
40k
REF B
310
VB
2mA
310
310
310
Figure 3.
The AD9066 is optimized to allow ac coupled inputs with a full-
scale input range of 500 mV
±
5%. An LSB weight is approxi-
mately 8 mV. The full-scale input range is defined as the voltage
range that accommodates 2
n
– 2 codes of equally weighted LSBs
(between the first and last code transitions). For the AD9066
there are 32 codes above and below the midscale voltage of the
A see Figure 3).
The full-scale input range of the AD9066 is equal to 500/620
×
(VT – VB), or nominally 500 mV. For dc coupled applications,
the REF A and REF B voltages can be used to feed back offset
compensation signals. This will allow the midscale transition
voltage of the ADCs to track supply and temperature variations.
In the event that offset correction signals are generated digitally,
the REF pins would not be required. Figure 4a shows the
equivalent circuit for the internal references. All component
tolerances are
±
25%.
V
S
40k
REF A
INPUT
1.4V THRESHOLD
a. Reference Circuit
V
S
b. Encode Input
V
S
OUTPUTS
40k
REF
c. Output Bits
d. Analog Input
Figure 4. Equivalent Circuits
–4–
REV. A
AD9066
Timing
ENCODE
866
866
+
INA
1/2
AD812
1/2
AD712
2k
+
1/2
AD712
866
ANALOG
INPUT
N
The duty cycle of the encode clock for the AD9066 is critical in
obtaining rated performance of the ADC. Rated maximum and
minimum pulse widths should be maintained, especially for
sample rates greater than 40 MSPS.
The AD9066 provides latched data outputs with three pipeline
delays. The length and load on the output data lines should be
minimized to reduce power supply transients inside the AD9066
which might diminish dynamic performance.
6 BITS
AD9066
REF A
OR REF B
+
LPF
LPF
866
2k
866
6 BITS
+15V
INB
t
A
N+1
N+2
866
+
ENCODE
1/2
AD812
–15V
t
V
D0–D5
VALID DATA
FOR N–3
VALID DATA
FOR N–2
VALID DATA
FOR N–1
Figure 6. Bipolar Input Using AD812 Drive for AD9066
t
PD
DATA
CHANGING
Figure 5. Timing Diagram
Layout should follow high frequency/high speed design guide-
lines. In addition the capacitance around the inverting input to
the AD812 should be minimized through a tight layout and the
use of low capacitance chip resistors for gain setting.
Quadrature Receiver Using the AD9066
The data is invalid during the period between t
V
and t
PD
. This
period refers to the time required for the AD9066 to fully switch
between valid CMOS logic levels. When latching the output
data, be careful to observe latch setup and hold time restrictions
as well as this data invalid period when designing the system
timing.
Layout and Signal Care
To insure optimum performance, a single low impedance
ground plane is recommended. Analog and digital grounds
should be connected together at the AD9066. Analog and digi-
tal power supplies should be bypassed, at the device, to ground
through 0.1
µF
ceramic capacitors.
The use of sockets may limit the dynamic performance of the
part and is not recommended except for prototype or evaluation
purposes.
Driving the AD9066 with a Bipolar Input
Although any type of input signal may be applied, the AD9066
has been optimized for low cost in-phase and quadrature (I and
Q) demodulators. Primary applications include digital direct
broadcast satellite applications where broadband quadrature
phase shift keying (QPSK) modulation is used. In these receivers
the recovered signal is separated into I and Q vector components
and digitized.
AD9066
ADC
IF IN
90
ADC
VCO
VCO
The analog input range of the AD9066 is between 3.7 V and
4.2 V. Because the input is offset, the normal method of driving
the analog input is to use a blocking capacitor between the ana-
log source and the AD9066 analog input pins. In applications
where DC coupling must be employed, the simple circuit shown
in Figure 6 will take a bipolar input and offset it to the operating
range of the AD9066.
To offset the input, the midpoint voltage of the AD9066 is buff-
ered off chip and then inverted with an AD712, a low input bias
current dual op amp. This inverted midpoint is then fed to a
summation amplifier that combines the bipolar input with the
inverted offset voltage. The summation amplifier is an AD812, a
wideband current feedback amplifier that provides good band-
width and low distortion.
Figure 7. Simplified Block Diagram
For data symbol rates less than 10 Mbaud, the AD607 IF/RF
receiver subsystem provides an ideal solution for the second
conversion stage of a complete receiver system. Figure 8 shows
the AD9066 and AD607 used together.
The AD607 accepts inputs as high as 500 MHz which may be
the output of the first IF stage or RF signals directly. The IF/RF
signal is mixed with the local oscillator to provide an IF fre-
quency of 400 kHz to 22 MHz. This signal is filtered externally
and then amplified with an on-chip AGC before being synchro-
nously demodulated with an on-chip PLL carrier recovery
circuit. The outputs are digitized with the AD9066. The digital
outputs may be processed with a DSP chip such as the ADSP-
2171, ADSP-21062, general purpose DSP or ASIC.
REV. A
–5–
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