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10-Bit, 210 MSPS TxDAC
®
D/A Converter
AD9740
FEATURES
High performance member of pin-compatible
TxDAC product family
Excellent spurious-free dynamic range performance
SNR @ 5 MHz output, 125 MSPS: 65 dB
Twos complement or straight binary data format
Differential current outputs: 2 mA to 20 mA
Power dissipation: 135 mW @ 3.3 V
Power-down mode: 15 mW @ 3.3 V
On-chip 1.2 V Reference
CMOS-compatible digital interface
28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP
packages
Edge-triggered latches
APPLICATIONS
Wideband communication transmit channel
Direct IF
Base stations
Wireless local loops
Digital radio links
Direct digital synthesis (DDS)
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
3.3V
REFLO
1.2V REF
REFIO
FS ADJ
DVDD
DCOM
CLOCK
CLOCK
SEGMENTED
SWITCHES
LSB
SWITCHES
LATCHES
150pF
AVDD
CURRENT
SOURCE
ARRAY
ACOM
0.1μF
AD9740
IOUTA
IOUTB
MODE
02911-001
R
SET
3.3V
SLEEP
DIGITAL DATA INPUTS (DB9–DB0)
Figure 1.
GENERAL DESCRIPTION
The AD9740
1
is a 10-bit resolution, wideband, third generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC
family, consisting of pin-compatible 8-, 10-, 12-, and 14-bit
DACs, is specifically optimized for the transmit signal path
of communication systems. All of the devices share the same
interface options, small outline package, and pinout, providing
an upward or downward component selection path based
on performance, resolution, and cost. The AD9740 offers
exceptional ac and dc performance while supporting update
rates up to 210 MSPS.
The AD9740’s low power dissipation makes it well suited for
portable and low power applications. Its power dissipation
can be further reduced to 60 mW with a slight degradation in
performance by lowering the full-scale current output. In
addition, a power-down mode reduces the standby power
dissipation to approximately 15 mW. A segmented current
source architecture is combined with a proprietary switching
technique to reduce spurious components and enhance
dynamic performance.
Edge-triggered input latches and a 1.2 V temperature-compensated
band gap reference have been integrated to provide a complete
monolithic DAC solution. The digital inputs support 3 V CMOS
logic families.
PRODUCT HIGHLIGHTS
1.
The AD9740 is the 10-bit member of the pin-compatible
TxDAC family, which offers excellent INL and DNL
performance.
Data input supports twos complement or straight binary
data coding.
High speed, single-ended CMOS clock input supports
210 MSPS conversion rate.
Low power: Complete CMOS DAC function operates on
135 mW from a 2.7 V to 3.6 V single supply. The DAC full-
scale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.
On-chip voltage reference: The AD9740 includes a 1.2 V
temperature-compensated band gap voltage reference.
Industry-standard 28-lead SOIC, 28-lead TSSOP, and 32-
lead LFCSP packages.
2.
3.
4.
5.
6.
1
Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
AD9740
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
Dynamic Specifications ............................................................... 5
Digital Specifications ................................................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Characteristics .............................................................. 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Terminology ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
Functional Description .................................................................. 13
Reference Operation .................................................................. 13
Reference Control Amplifier .................................................... 14
DAC Transfer Function ............................................................. 14
Analog Outputs .......................................................................... 14
Digital Inputs .............................................................................. 15
Clock Input.................................................................................. 15
DAC Timing................................................................................ 16
Power Dissipation....................................................................... 16
Applying the AD9740 ................................................................ 17
Differential Coupling Using a Transformer............................... 17
Differential Coupling Using an Op Amp................................ 18
Single-Ended, Unbuffered Voltage Output............................. 18
Single-Ended, Buffered Voltage Output Configuration........ 18
Power and Grounding Considerations, Power Supply
Rejection...................................................................................... 19
Evaluation Board ............................................................................ 20
General Description................................................................... 20
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 31
Rev. B | Page 2 of 32
AD9740
REVISION HISTORY
12/05—Rev. A to Rev. B
Updated Format.................................................................. Universal
Changes to General Description and Product Highlights...........1
Changes to Table 1 ............................................................................4
Changes to Table 2 ............................................................................5
Changes to Table 5 ............................................................................8
Changes to Figure 6.........................................................................10
Inserted Figure 11; Renumbered Sequentially ............................10
Changes to Figure 12, Figure 13, Figure 14, and Figure 15 .......11
Changes to Functional Description and Reference
Operation Sections..........................................................................13
Inserted Figure 23; Renumbered Sequentially ............................13
Changes to DAC Transfer Function Section and Figure 25 ......14
Changes to Digital Inputs Section.................................................15
Changes to Figure 30 and Figure 31 .............................................17
Updated Outline Dimensions........................................................30
Changes to Ordering Guide...........................................................31
5/03—Rev. 0 to Rev. A
Added 32-Lead LFCSP Package ....................................... Universal
Edits to Features ................................................................................1
Edits to Product Highlights .............................................................1
Edits to DC Specifications ...............................................................2
Edits to Dynamic Specifications .....................................................3
Edits to Digital Specifications..........................................................4
Edits to Absolute Maximum Ratings..............................................5
Edits to Thermal Characteristics ....................................................5
Edits to Ordering Guide...................................................................5
Edits to Pin Configuration...............................................................6
Edits to Pin Function Descriptions ................................................6
Edits to Figure 2 ................................................................................7
Replaced TPCs 1, 4, 7, and 8............................................................8
Edits to Figure 3 ..............................................................................10
Edits to Functional Description Section ......................................10
Edits to Digital Inputs Section.......................................................12
Added Clock Input Section............................................................12
Added Figure 7 ................................................................................12
Edits to DAC Timing Section........................................................12
Edits to Sleep Mode Operation Section .......................................13
Edits to Power Dissipation Section...............................................13
Renumbered Figures 8 to 26..........................................................13
Added Figure 11 ..............................................................................13
Added Figures 27 to 35...................................................................21
Updated Outline Dimensions........................................................26
5/02—Revision 0: Initial Version
Rev. B | Page 3 of 32
AD9740
SPECIFICATIONS
DC SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
OUTFS
= 20 mA, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DC ACCURACY
1
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current
2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current
3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance (External Reference)
Small Signal Bandwidth
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
AVDD
DVDD
CLKVDD
Analog Supply Current (I
AVDD
)
Digital Supply Current (I
DVDD
)
4
Clock Supply Current (I
CLKVDD
)
Supply Current Sleep Mode (I
AVDD
)
Power Dissipation
4
Power Dissipation
5
Power Supply Rejection Ratio—AVDD
6
Power Supply Rejection Ratio—DVDD
6
OPERATING RANGE
1
2
Min
10
−0.7
−0.5
−0.02
−2
−2
2
−1
Typ
Max
Unit
Bits
LSB
LSB
% of FSR
% of FSR
% of FSR
mA
V
kΩ
pF
V
nA
V
kΩ
MHz
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
±0.15
±0.12
+0.7
+0.5
+0.02
+2
+2
20
+1.25
±0.1
±0.1
100
5
1.14
1.20
100
1.26
0.1
7
0.5
0
±50
±100
±50
1.25
2.7
2.7
2.7
3.3
3.3
3.3
33
8
5
5
135
145
3.6
3.6
3.6
36
9
6
6
145
+1
+0.04
+85
−1
−0.04
−40
V
V
V
mA
mA
mA
mA
mW
mW
% of FSR/V
% of FSR/V
°C
Measured at IOUTA, driving a virtual ground.
Nominal full-scale current, I
OUTFS
, is 32 times the I
REF
current.
3
An external buffer amplifier with input bias current <100 nA should be used to drive any external load.
4
Measured at f
CLOCK
= 25 MSPS and f
OUT
= 1 MHz.
5
Measured as unbuffered voltage output with I
OUTFS
= 20 mA, 50 Ω R
LOAD
at IOUTA and IOUTB, f
CLOCK
= 100 MSPS, and f
OUT
= 40 MHz.
6
±5% power supply variation.
Rev. B | Page 4 of 32
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