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FEATURES
Member of Pin-Compatible TxDAC Product Family
125 MSPS Update Rate
10-Bit Resolution
Excellent Spurious Free Dynamic Range Performance
SFDR to Nyquist @ 40 MHz Output: 52 dBc
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V
Power-Down Mode: 25 mW @ 5 V
On-Chip 1.20 V Reference
Single +5 V or +3 V Supply Operation
Packages: 28-Lead SOIC and TSSOP
Edge-Triggered Latches
APPLICATIONS
Communication Transmit Channel:
Basestations
Set Top Boxes
Digital Radio Link
Direct Digital Synthesis (DDS)
Instrumentation
PRODUCT DESCRIPTION
0.1 F
10-Bit, 125 MSPS
TxDAC
®
D/A Converter
AD9760
FUNCTIONAL BLOCK DIAGRAM
+5V
0.1 F
REFLO
+1.20V REF
50pF
REFIO
FS ADJ
R
SET
+5V
DVDD
DCOM
CLOCK
CLOCK
SLEEP
DIGITAL DATA INPUTS (DB9–DB0)
SEGMENTED
SWITCHES
LSB
SWITCHES
CURRENT
SOURCE
ARRAY
COMP1
AVDD
ACOM
AD9760
COMP2
0.1 F
I
OUTA
I
OUTB
LATCHES
The AD9760 and AD9760-50 are the 10-bit resolution members
of the TxDAC series of high performance, low power CMOS
digital-to-analog converters (DACs). The AD9760-50 is a lower
performance option that is guaranteed and specified for 50 MSPS
operation. The TxDAC family that consists of pin compatible 8-,
10-, 12- and 14-bit DACs is specifically optimized for the trans-
mit signal path of communication systems. All of the devices
share the same interface options, small outline package and
pinout, thus providing an upward or downward component
selection path based on performance, resolution and cost. Both
the AD9760 and AD9760-50 offer exceptional ac and dc
performance while supporting update rates up to 125 MSPS
and 60 MSPS respectively.
The AD9760’s flexible single-supply operating range of 2.7 V to
5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 45 mW without a significant degradation in
performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 25 mW.
The AD9760 is manufactured on an advanced CMOS process. A
segmented current source architecture is combined with a propri-
etary switching technique to reduce spurious components and
enhance dynamic performance. Edge-triggered input latches and a
1.2 V temperature compensated bandgap reference have been inte-
grated to provide a complete monolithic DAC solution. Flexible
supply options support +3 V and +5 V CMOS logic families.
TxDAC is a registered trademark of Analog Devices, Inc.
The AD9760 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 kΩ output impedance.
Differential current outputs are provided to support single-
ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen-
tary, single-ended voltage outputs or fed directly into a trans-
former. The output voltage compliance range is 1.25 V.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9760 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier that provides a wide
(>10:1) adjustment span allows the AD9760 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9760 may oper-
ate at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.
The AD9760 is available in a 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTS
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
1. The AD9760 is a member of the TxDAC product family that
provides an upward or downward component selection path
based on resolution (8 to 14 bits), performance and cost.
2. Manufactured on a CMOS process, the AD9760 uses a pro-
prietary switching technique that enhances dynamic perfor-
mance beyond what was previously attainable by higher
power/cost bipolar or BiCMOS devices.
3. On-chip, edge-triggered input CMOS latches interface readily
to +3 V and +5 V CMOS logic families. The AD9760 can
support update rates up to 125 MSPS.
4. A flexible single-supply operating range of 2.7 V to 5.5 V and
a wide full-scale current adjustment span of 2 mA to 20 mA
allow the AD9760 to operate at reduced power levels.
5. The current output(s) of the AD9760 can be easily config-
ured for various single-ended or differential circuit topologies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD9760/AD9760-50–SPECIFICATIONS
DC SPECIFICATIONS
(T
Parameter
RESOLUTION
DC ACCURACY
1
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
MONOTONICITY
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current
2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current
3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
Small Signal Bandwidth (w/o C
COMP1
)
4
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
AVDD
5
DVDD
Analog Supply Current (I
AVDD
)
Digital Supply Current (I
DVDD
)
6
Supply Current Sleep Mode (I
AVDD
)
Power Dissipation
6
(5 V, I
OUTFS
= 20 mA)
Power Dissipation
7
(5 V, I
OUTFS
= 20 mA)
Power Dissipation
7
(3 V, I
OUTFS
= 2 mA)
Power Supply Rejection Ratio—AVDD
Power Supply Rejection Ratio—DVDD
OPERATING RANGE
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, unless otherwise noted)
Min
10
–1.0
–0.5
±
0.5
±
0.25
+1.0
+0.5
Typ
Max
Units
Bits
LSB
LSB
Guaranteed Over Specified Temperature Range
–0.025
–10
–10
2.0
–1.0
+0.025
+10
+10
20.0
1.25
% of FSR
% of FSR
% of FSR
mA
V
kΩ
pF
V
nA
V
MΩ
MHz
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
±
2
±
1
100
5
1.08
1.20
100
1.32
0.1
1
1.4
0
±
50
±
100
±
50
1.25
2.7
2.7
5.0
5.0
25
3
140
190
45
5.5
5.5
30
5
8.5
175
–0.04
–0.025
–40
+0.04
+0.025
+85
V
V
mA
mA
mA
mW
mW
mW
% of FSR/V
% of FSR/V
°C
NOTES
1
Measured at I
OUTA
, driving a virtual ground.
2
Nominal full-scale current, I
OUTFS
, is 32
×
the I
REF
current.
3
Use an external buffer amplifier to drive any external load.
4
Reference bandwidth is a function of external cap at COMP1 pin and signal level. Refer to Figure 41.
5
For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.
6
Measured at f
CLOCK
= 50 MSPS and f
OUT
= 1.0 MHz.
7
Measured as unbuffered voltage output into 50
Ω
R
LOAD
at I
OUTA
and I
OUTB
, f
CLOCK
= 100 MSPS and f
OUT
= 40 MHz.
Specifications subject to change without notice.
–2–
REV. B
AD9760
DYNAMIC SPECIFICATIONS
Model
Parameter
DYNAMIC PERFORMANCE
Maximum Output Update Rate (f
CLOCK
)
Output Settling Time (t
ST
) (to 0.1%)
1
Output Propagation Delay (t
PD
)
Glitch Impulse
Output Rise Time (10% to 90%)
1
Output Fall Time (10% to 90%)
1
Output Noise (I
OUTFS
= 20 mA)
Output Noise (I
OUTFS
= 2 mA)
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
f
CLOCK
= 50 MSPS; f
OUT
= 1.00 MHz
T
A
= +25°C
T
MIN
to T
MAX
f
CLOCK
= 50 MSPS; f
OUT
= 2.51 MHz
f
CLOCK
= 50 MSPS; f
OUT
= 5.02 MHz
f
CLOCK
= 50 MSPS; f
OUT
= 20.2 MHz
f
CLOCK
= 100 MSPS; f
OUT
= 2.51 MHz
f
CLOCK
= 100 MSPS; f
OUT
= 5.04 MHz
f
CLOCK
= 100 MSPS; f
OUT
= 20.2 MHz
f
CLOCK
= 100 MSPS; f
OUT
= 40.4 MHz
Spurious-Free Dynamic Range within a Window
f
CLOCK
= 50 MSPS; f
OUT
= 1.00 MHz
T
A
= +25°C
T
MIN
to T
MAX
f
CLOCK
= 50 MSPS; f
OUT
= 5.02 MHz; 2 MHz Span
f
CLOCK
= 100 MSPS; f
OUT
= 5.04 MHz; 4 MHz Span
Total Harmonic Distortion
f
CLOCK
= 50 MSPS; f
OUT
= 1.00 MHz
T
A
= +25°C
T
MIN
to T
MAX
f
CLOCK
= 50 MHz; f
OUT
= 2.00 MHz
f
CLOCK
= 100 MHz; f
OUT
= 2.00 MHz
NOTES
1
Measured single ended into 50
Ω
load.
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA, Differential Transformer Coupled Output,
50 Doubly Terminated, unless otherwise noted)
Min
125
35
1
5
2.5
2.5
50
30
AD9760
Typ
Max
Min
50
AD9760-50
Typ
Max
60
35
1
5
2.5
2.5
50
30
Units
MSPS
ns
ns
pV-s
ns
ns
pA/√Hz
pA/√Hz
70
68
73
73
68
55
74
68
60
52
68
66
73
73
68
55
N/A
N/A
N/A
N/A
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
74
72
78
76
76
72
70
78
76
N/A
dBc
dBc
dBc
dBc
–76
–71
–71
–73
–71
–76
–71
N/A
–70
–68
dBc
dBc
dBc
dBc
REV. B
–3–
AD9760
DIGITAL SPECIFICATIONS
(T
Parameter
DIGITAL INPUTS
Logic “1” Voltage @ DVDD = +5 V
Logic “1” Voltage @ DVDD = +3 V
Logic “0” Voltage @ DVDD = +5 V
Logic “0” Voltage @ DVDD = +3 V
Logic “1” Current
Logic “0” Current
Input Capacitance
Input Setup Time (t
S
)
Input Hold Time (t
H
)
Latch Pulsewidth (t
LPW
)
Specification subject to change without notice.
DB0–DB9
MIN
to T
MAX
, AVDD = +5 V, DVDD = +5 V, I
OUTFS
= 20 mA unless otherwise noted)
Min
3.5
2.1
Typ
5
3
0
0
Max
Units
V
V
V
V
µA
µA
pF
ns
ns
ns
–10
–10
5
2.0
1.5
3.5
1.3
0.9
+10
+10
t
S
CLOCK
t
H
t
LPW
t
PD
t
ST
0.1%
0.1%
I
OUTA
OR
I
OUTB
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
Parameter
AVDD
DVDD
ACOM
AVDD
CLOCK, SLEEP
Digital Inputs
I
OUTA
, I
OUTB
COMP1, COMP2
REFIO, FSADJ
REFLO
Junction Temperature
Storage Temperature
Lead Temperature
(10 sec)
With
Respect to
ACOM
DCOM
DCOM
DVDD
DCOM
DCOM
ACOM
ACOM
ACOM
ACOM
Min
–0.3
–0.3
–0.3
–6.5
–0.3
–0.3
–1.0
–0.3
–0.3
–0.3
–65
Max
+6.5
+6.5
+0.3
+6.5
DVDD + 0.3
DVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
+0.3
+150
+150
+300
Units
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
ORDERING GUIDE
Model
AD9760AR
AD9760ARU
AD9760AR50
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package
Descriptions
28-Lead 300 mil
SOIC
28-Lead 170 mil
TSSOP
28-Lead 300 mil
SOIC
28-Lead 170 mil
TSSOP
Package
Options
R-28
RU-28
R-28
RU-28
AD9760ARU50 –40°C to +85°C
AD9760-EB
Evaluation Board
THERMAL CHARACTERISTICS
Thermal Resistance
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
28-Lead 300 mil (7.5 mm) SOIC
θ
JA
= 71.4°C/W
θ
JC
= 23°C/W
28-Lead 170 mil (4.4 mm) TSSOP
θ
JA
= 97.9°C/W
θ
JC
= 14.0°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9760 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. B
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