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MT5C1005C-20E/883C

Description
Standard SRAM, 256KX4, 20ns, CMOS, CDIP28, 0.400 INCH, CERAMIC, DIP-28
Categorystorage    storage   
File Size89KB,8 Pages
ManufacturerMicross
Websitehttps://www.micross.com
Download Datasheet Parametric View All

MT5C1005C-20E/883C Overview

Standard SRAM, 256KX4, 20ns, CMOS, CDIP28, 0.400 INCH, CERAMIC, DIP-28

MT5C1005C-20E/883C Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMicross
Parts packaging codeDIP
package instructionDIP,
Contacts28
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Maximum access time20 ns
JESD-30 codeR-CDIP-T28
JESD-609 codee0
length35.56 mm
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width4
Number of functions1
Number of ports1
Number of terminals28
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize256KX4
Output characteristics3-STATE
ExportableYES
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Filter levelMIL-STD-883
Maximum seat height4.31 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width10.16 mm
AUSTIN SEMICONDUCTOR, INC.
MT5C1005 883C
256K x 4 SRAM
SRAM
AVAILABLE AS MILITARY
SPECIFICATIONS
• MIL-STD-883
256K x 4 SRAM
PIN ASSIGNMENT (Top View)
28-Pin DIP
(400 MIL)
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
CE
OE
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
A6
A5
A4
A3
A2
A1
A0
NC
DQ4
DQ3
DQ2
DQ1
WE
A7
A8
A9
A12
A10
A11
A13
NC
A14
A15
A16
A17
NC
CE
OE
Vss
FEATURES
High speed: 15, 20, 25, 35 and 45ns
Battery Backup: 2V data retention
Low power standby
High-performance, low-power, CMOS double-metal
process
• Single +5V (±10%) power supply
• Easy memory expansion with
/
C
/
E and
/
O
/
E options
• All inputs and outputs are TTL compatible
32-Pin LCC
32-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A6
A5
A2
A4
A3
A1
NC
NC
A0
NC
DQ4
DQ3
DQ2
DQ1
WE
OPTIONS
• Timing
15ns access (Contact factory)
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
• Packages
Ceramic DIP (400 mil)
Ceramic Flat Pack
Ceramic LCC
Ceramic SOJ
Ceramic Quad LCC (Contact factory)
MARKING
-15
-20
-25
-35
-45
-55*
-70*
C
F
EC
DCJ
ECW
L
E
No. 109
No. 303
No. 207
No. 501
No. 206
A7
A8
A9
A12
A10
A11
A13
NC
A14
A15
A16
A17
NC
CE
OE
Vss
32-Pin Flat Pack
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A6
A5
A2
A4
A3
A1
NC
NC
A0
NC
DQ4
DQ3
DQ2
DQ1
WE
32-Pin LCC
A7
A9
A12
A8
A14
A7
NC
NC
Vcc
V
CC
WE
A6
A13
A5
4 3 2 1 32 31 30
A6
A10
5
A11
A5
A11
6
A12
A4
A12
7
A13
A3
A13
8
A14
A2
A14
9
A15
A1
A16
N15
10
A0
A17
A16
11
NC
CE
A17
12
DQ1
OE
13
CE
14 15 16 17 18 19 20
A2
A8
29
A2
A4
A9
28
A4
A3
A11
27
A3
A1
NC
26
A1
A0
OE
25
NC
NC
A10
24
NC
CE
23
A0
NC
DQ8
22
NC
NC
DQ7
21
DQ4
• 2V data retention, low power standby
• Radiation Tolerant (Epi)
*Electrical characteristics identical to those provided for the 45ns
access devices.
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs high-
speed, low-power CMOS designs using a four transistor
memory cell. Austin Semiconductor SRAMs are fabricated
using double-layer metal, double-layer polysilicon tech-
nology.
For flexibility in high-speed memory applications, Aus-
tin Semiconductor offers chip enable (/C
/
E) and output en-
able (?O
/
E) capability. These enhancements can place the
outputs in High-Z for additional flexibility in system
design. Writing to these devices is accomplished when
MT5C1005 883C
REV. 11/97
DS000005
write enable (
?
W
/
E) and
/
C
/
E inputs are both LOW. Reading
is accomplished when
/
W
/
E remains HIGH while
/
C
/
E and
?
O
/
E go LOW. The devices offer a reduced power standby
mode when disabled. This allows system designs to achieve
low standby power requirements.
The “L” version provides an approximate 50 percent
reduction in CMOS standby current (I
SBC2
) over the stan-
dard version.
All devices operate from a single +5V power supply and
all inputs and outputs are fully TTL compatible.
1-57
Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.
DQ2
NC
DQ3
OE
Vss
V
SS
NC
WE
DQ4
DQ1
DQ5
DQ2
DQ6
DQ3
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