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M5A3-128/120-10YC

Description
EE PLD, 10ns, 128-Cell, CMOS, PQFP160, PLASTIC, QFP-160
CategoryProgrammable logic devices    Programmable logic   
File Size666KB,47 Pages
ManufacturerLattice
Websitehttp://www.latticesemi.com
Download Datasheet Parametric View All

M5A3-128/120-10YC Overview

EE PLD, 10ns, 128-Cell, CMOS, PQFP160, PLASTIC, QFP-160

M5A3-128/120-10YC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerLattice
Parts packaging codeQFP
package instructionPLASTIC, QFP-160
Contacts160
Reach Compliance Codecompliant
ECCN codeEAR99
Other featuresYES
maximum clock frequency83.3 MHz
In-system programmableYES
JESD-30 codeS-PQFP-G160
JESD-609 codee0
JTAG BSTYES
length28 mm
Humidity sensitivity level3
Dedicated input times
Number of I/O lines120
Number of macro cells128
Number of terminals160
Maximum operating temperature70 °C
Minimum operating temperature
organize0 DEDICATED INPUTS, 120 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeQFP160,1.2SQ
Package shapeSQUARE
Package formFLATPACK
power supply3.3 V
Programmable logic typeEE PLD
propagation delay10 ns
Certification statusNot Qualified
Maximum seat height4.1 mm
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
width28 mm
MACH 5 CPLD Family
Fifth Generation MACH Architecture
FEATURES
x
High logic densities and I/Os for increased logic integration
x
x
x
x
x
x
x
— 128 to 512 macrocell densities
— 68 to 256 I/Os
Wide selection of density and I/O combinations to support most application needs
— 6 macrocell density options
— 7 I/O options
— Up to 4 I/O options per macrocell density
— Up to 5 density & I/O options for each package
Performance features to fit system needs
— 5.5 ns t
PD
Commercial, 7.5 ns t
PD
Industrial
— 182 MHz f
CNT
— Four programmable power/speed settings per block
Flexible architecture facilitates logic design
— Multiple levels of switch matrices allow for performance-based routing
— 100% routability and pin-out retention
— Synchronous and asynchronous clocking, including dual-edge clocking
— Asynchronous product- or sum-term set or reset
— 16 to 64 output enables
— Functions of up to 32 product terms
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— IEEE 1149.1 compliant for boundary scan testing
— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port
— PCI compliant (-5/-6/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system design
— Bus-Friendly™ Inputs & I/Os
— Individual output slew rate control
— Hot socketing
— Programmable security bit
Advanced E
2
CMOS process provides high performance, cost effective solutions
Supported by ispDesignEXPERT™ software for rapid logic development
— Supports HDL design methodologies with results optimized for MACH 5 devices
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
Lattice and Third-party hardware programming support
— LatticePRO™ software for in-system programmability support on PCs and Automated Test
Equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
Publication#
20446
Amendment/0
Rev:
I
Issue Date:
September 2000
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