EM260
ZigBee/802.15.4 Network Processor
This datasheet applies to EmberZNet PRO 3.1 or
greater.
Integrated 2.4GHz, IEEE 802.15.4-compliant transceiver:
Standard SPI or UART Interfaces allow
for connection to a variety of Host
microcontrollers
Robust RX filtering allows co-existence with IEEE
802.11g and Bluetooth devices
- 99dBm RX sensitivity (1% PER, 20byte packet)
+ 2.5dBm nominal output power
Increased radio performance mode (boost mode)
gives – 100dBm sensitivity and + 4.5dBm
transmit power
Integrated VCO and loop filter
Secondary TX-only RF port for applications
requiring external PA.
Non-intrusive debug interface (SIF)
Integrated hardware and software support for
the Ember development environment
Dedicated peripherals and integrated memory
Provides integrated RC oscillator for low
power operation
Three sleep modes:
Processor idle (automatic)
Deep sleep—1.0
μA
Power down—1.0
μA
Integrated IEEE 802.15.4 PHY and MAC
ZigBee-compliant stack running on the dedicated
network processor
Controlled by the Host using the EmberZNet Serial
Protocol (EZSP)
Watchdog timer and power-on-reset circuitry
Integrated AES encryption accelerator
Integrated 1.8V voltage regulator
TX_ACTIVE
PA select
RF_TX_ALT_P,N
PA
SYNTH
PA
DAC
MAC
+
Baseband
PacketTrace
RF_P,N
BIAS_R
OSCA
LNA
Bias
IF
ADC
Network
Processor
(XAP2b)
Encryption acclerator
HF OSC
Network Processor
Peripherals
Integrated Flash and RAM
OSCB
Internal
RC-OSC
Serial
Controller
Interrupt
Controller
Always
powered
Sleep
timer
Watchdog
POR
nRESET
SIF_CLK
SIF
VREG_OUT
Regulator
Chip
manager
SIF_MISO
SIF_MOSI
nSIF_LOAD
IO Controller
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
www.silabs.com
May 29, 2013
120-0260-000M Rev 1.1
nRTS
nSSEL_INT/nCTS
MOSI
nSSEL
SCLK
MISO
nHOST_INT/RXD
nWAKE
PTI_DATA
PTI_EN
SDBG
LINK_ACTIVITY
TXD
EM260
General Description
Note:
Several important sections have been moved into standalone documents. Section 6 describing the
ASH protocol has been moved to document UG101,
UART Gateway Protocol Reference.
Section 7 on
EZSP has been moved to document UG100,
EZSP Reference Guide.
The EM260 integrates a 2.4GHz, IEEE 802.15.4-compliant transceiver with a 16-bit network processor (XAP2b
core) to run EmberZNet PRO, Silicon Labs’ ZigBee-compliant network stack. The EM260 exposes access to the
EmberZNet PRO API across a standard SPI module or a UART module, allowing application development on a
Host platform. This means that the EM260 can be viewed as a ZigBee peripheral connected over a serial
interface. The XAP2b microprocessor is a power-optimized core integrated in the EM260. It contains
integrated Flash and RAM memory along with an optimized peripheral set to enhance the operation of the
network stack.
The transceiver utilizes an efficient architecture that exceeds the dynamic range requirements imposed by
the IEEE 802.15.4-2003 standard by over 15dB. The integrated receive channel filtering allows for co-existence
with other communication standards in the 2.4GHz spectrum such as IEEE 802.11g and Bluetooth. The
integrated regulator, VCO, loop filter, and power amplifier keep the external component count low. An
optional high-performance radio mode (boost mode) is software selectable to boost dynamic range by a
further 3dB.
The EM260 contains embedded Flash and integrated RAM for program and data storage. By employing an
effective wear-leveling algorithm, the stack optimizes the lifetime of the embedded Flash, and affords the
application the ability to configure stack and application tokens within the EM260.
To maintain the strict timing requirements imposed by ZigBee and the IEEE 802.15.4-2003 standard, the EM260
integrates a number of MAC functions into the hardware. The MAC hardware handles automatic ACK
transmission and reception, automatic backoff delay, and clear channel assessment for transmission, as well
as automatic filtering of received packets. In addition, the EM260 allows for true MAC level debugging by
integrating the Packet Trace Interface.
An integrated voltage regulator, power-on-reset circuitry, sleep timer, and low-power sleep modes are
available. The deep sleep and power down modes draw less than 1μA, allowing products to achieve long
battery life.
Finally, the EM260 utilizes the non-intrusive SIF module for powerful software debugging and programming of
the network processor.
Target applications for the EM260 include:
Building automation and control
Home automation and control
Home entertainment control
Asset tracking
The EM260 can only be purchased with the EmberZNet PRO stack. This technical datasheet details the EM260
features available to customers using it with the EmberZNet PRO stack.
120-0260-000M Rev 1.1
Page 2
EM260
Contents
1
2
3
3.1
3.2
3.3
3.4
3.5
3.6
Pin Assignments
Top-Level Functional Description
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Environmental Characteristics
DC Electrical Characteristics
Digital I/O Specifications
RF Electrical Characteristics
3.6.1
Receive
3.6.2
Transmit
3.6.3
Synthesizer
4
7
9
9
9
10
11
12
13
13
14
14
5.2
SPI Transaction
5.2.1
Command Section
5.2.2
Wait Section
5.2.3
Response Section
5.2.4
Asynchronous Signaling
5.2.5
Spacing
5.2.6
Waking the EM260 from Sleep
5.2.7
Error Conditions
SPI Protocol Timing
Data Format
SPI Byte
5.5.1
Primary SPI Bytes
5.5.2
Special Response Bytes
22
23
23
23
23
24
24
24
25
26
27
27
28
5.3
5.4
5.5
4
4.1
Functional Description
Receive (RX) Path
4.1.1
RX Baseband
4.1.2
RSSI and CCA
Transmit (TX) Path
4.2.1
TX Baseband
4.2.2
TX_ACTIVE Signal
Integrated MAC Module
Packet Trace Interface (PTI)
XAP2b Microprocessor
Embedded Memory
4.6.1
Simulated EEPROM
4.6.2
Flash Information Area (FIA)
Encryption Accelerator
nRESET Signal
Reset Detection
15
15
15
15
16
16
16
16
17
17
17
17
18
18
18
18
18
5.6
Powering On, Power Cycling, and Rebooting28
5.6.1
Bootloading the EM260
29
5.6.2
Unexpected Resets
29
Transaction Examples
29
5.7.1
SPI Protocol Version
30
5.7.2
EmberZNet Serial Protocol Frame—
Version Command
31
5.7.3
EM260 Reset
32
5.7.4
Three-Part Transaction: Wake, Get
Version, Stack Status Callback
33
5.7
4.2
4.3
4.4
4.5
4.6
6
7
8
9
10
11
12
13
14
15
16
UART Gateway Protocol
35
SIF Module Programming and Debug
Interface
37
Typical Application
Mechanical Details
QFN40 Footprint
Part Marking
Ordering Information
Shipping Box Label
Abbreviations and Acronyms
References
Revision History
38
40
42
43
44
45
46
48
49
4.7
4.8
4.9
4.10
Power-on-Reset (POR)
4.11
Clock Sources
19
4.11.1
High-Frequency Crystal Oscillator 19
4.11.2
Internal RC Oscillator
20
4.12
Random Number Generator
4.13
Watchdog Timer
4.14
Sleep Timer
4.15
Power Management
20
21
21
21
5
5.1
SPI Protocol
Physical Interface Configuration
22
22
Page 3
120-0260-000M Rev 1.1
EM260
1 Pin Assignments
VDD_SYNTH_PRE
LINK_ACTIVITY
VDD_24MHZ
VDD_FLASH
32
VDD_CORE
nWAKE
OSCA
OSCB
SDBG
40
VDD_VCO
RF_P
RF_N
VDD_RF
RF_TX_ALT_P
RF_TX_ALT_N
VDD_IF
BIAS_R
VDD_PADSA
TX_ACTIVE
1
2
3
4
5
6
7
8
9
10
11
39
38
37
36
35
34
33
31
30
29
28
27
nSIF_LOAD
SIF_MOSI
SIF_MISO
SIF_CLK
nHOST_INT
N.C.
VDD_PADS
PTI_DATA
PTI_EN
nSSEL
41
GND
EM260
GND
26
25
24
23
22
21
20
31
30
29
28
27
nSIF_LOAD
SIF_MOSI
SIF_MISO
SIF_CLK
RXD
TXD
VDD_PADS
PTI_DATA
PTI_EN
N.C.
GND
26
25
24
23
22
21
20
N.C.
SCLK
12
13
14
15
16
17
18
19
nRESET
VREG_OUT
nSSEL_INT
VDD_PADS
VDD_CORE
Figure 1. EM260 Pin Assignment for SPI Protocol
VDD_SYNTH_PRE
LINK_ACTIVITY
VDD_24MHZ
40
VDD_VCO
RF_P
RF_N
VDD_RF
RF_TX_ALT_P
RF_TX_ALT_N
VDD_IF
BIAS_R
VDD_PADSA
TX_ACTIVE
1
2
3
4
5
6
7
8
9
10
11
39
38
37
36
35
34
33
32
41
GND
EM260
12
13
14
15
16
17
18
19
nRESET
VREG_OUT
VDD_PADS
Figure 2. EM260 Pin Assignment for UART Protocol
120-0260-000M Rev 1.1
Page 4
VDD_CORE
VDD_PADS
nCTS
nRTS
N.C.
N.C.
VDD_FLASH
VDD_CORE
OSCA
OSCB
SDBG
N.C.
VDD_PADS
N.C.
MISO
MOSI
EM260
Table 1. Pin Descriptions
Pin #
1
2
3
4
5
6
7
8
9
10
Signal
VDD_VCO
RF_P
RF_N
VDD_RF
RF_TX_ALT_P
RF_TX_ALT_N
VDD_IF
BIAS_R
VDD_PADSA
TX_ACTIVE
Directio
n
Power
I/O
I/O
Power
O
O
Power
I
Power
O
Description
1.8V VCO supply; should be connected to VREG_OUT
Differential (with RF_N) receiver input/transmitter output
Differential (with RF_P) receiver input/transmitter output
1.8V RF supply (LNA and PA); should be connected to VREG_OUT
Differential (with RF_TX_ALT_N) transmitter output (optional)
Differential (with RF_TX_ALT_P) transmitter output (optional)
1.8V IF supply (mixers and filters); should be connected to VREG_OUT
Bias setting resistor
Analog pad supply (1.8V); should be connected to VREG_OUT
Logic-level control for external RX/TX switch
The EM260 baseband controls TX_ACTIVE and drives it high (1.8V) when in TX mode.
(Refer to Table 6 and section 4.2.2.)
11
12
13
14
15
nRESET
VREG_OUT
VDD_PADS
VDD_CORE
nSSEL_INT
nCTS
16
N.C.
nRTS
17
MOSI
N.C.
18
MISO
N.C.
19
20
VDD_PADS
SCLK
N.C.
21
nSSEL
N.C.
22
23
PTI_EN
PTI_DATA
I
Power
Power
Power
I
I
I
O
I
I
O
I
Power
I
I
I
I
O
O
Active low chip reset (internal pull-up)
Regulator output (1.8V)
Pads supply (2.1 – 3.6V)
1.8V digital core supply; should be connected to VREG_OUT
SPI Slave Select Interrupt (from Host to EM260)
When using the SPI interface, this signal must be connected to nSSEL (Pin 21)
UART Clear To Send (enables EM260 transmission)
When using the UART interface, this signal should be left unconnected if not used.
When using the SPI interface, this signal is left not connected.
UART Request To Send (enables Host transmission)
When using the UART interface, this signal should be left unconnected if not used.
SPI Data, Master Out / Slave In (from Host to EM260)
When using the UART interface, this signal is left not connected.
SPI Data, Master In / Slave Out (from EM260 to Host)
When using the UART interface, this signal is left not connected.
Pads supply (2.1 – 3.6V)
SPI Clock (from Host to EM260)
When using the UART interface, this signal is left not connected.
SPI Slave Select (from Host to EM260)
When using the UART interface, this signal is left not connected.
Frame signal of Packet Trace Interface (PTI)
Data signal of Packet Trace Interface (PTI)
Page 5
120-0260-000M Rev 1.1
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