Features
•
Serial Peripheral Interface (SPI) Compatible
•
Supports SPI Modes 0 (0,0) and 3 (1,1)
•
Medium-voltage and Standard-voltage Operation
•
•
•
•
•
•
•
– 5.0 (V
CC
= 4.5V to 5.5V)
– 2.7 (V
CC
= 2.7V to 5.5V)
3 MHz Clock Rate
64-byte Page Mode and Byte Write Operation
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for
both Hardware and Software Data Protection
Self-timed Write Cycle (5 ms Typical)
High-reliability
– Endurance: 100,000 Write Cycles
– Data Retention: >200 Years
8-lead PDIP, 8-lead JEDEC SOIC and 8-lead EIAJ SOIC Packages
SPI Serial
Automotive
EEPROMs
128K (16,384 x 8)
256K (32,768 x 8)
Description
The AT25128/256 provides 131,072/262,144 bits of serial electrically-erasable pro-
grammable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits
each. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available in
space saving 8-lead PDIP (AT25128/256), 8-lead JEDEC SOIC (AT25128) and 8-lead
EIAJ SOIC (AT25256) packages. In addition, the entire family is available in 5.0V
(4.5V to 5.5V) and 2.7V (2.7V to 5.5V) versions.
AT25128
AT25256
Pin Configurations
Pin Name
CS
SCK
SI
SO
GND
VCC
WP
HOLD
NC
DC
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Write Protect
Suspends Serial Input
No Connect
Don't Connect
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
8-lead PDIP
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
8-lead SOIC
Rev. 3262C–SEEPR–6/03
1
The AT25128/256 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data
Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no sep-
arate ERASE cycle is required before WRITE.
BLOCK WRITE protection is enabled by programming the status register with top ¼, top ½ or entire array of write protec-
tion. Separate program enable and program disable instructions are provided for additional data protection. Hardware data
protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may
be used to suspend any serial communication without resetting the serial sequence.
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
Block Diagram
16384/32768 x 8
2
AT25128/256
3262C–SEEPR–6/03
AT25128/256
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25°C, f = 1.0 MHz, V
CC
= +5.0V (unless otherwise noted).
Symbol
C
OUT
C
IN
Note:
Test Conditions
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
1. This parameter is characterized and is not 100% tested.
Max
8
6
Units
pF
pF
Conditions
V
OUT
= 0V
V
IN
= 0V
DC Characteristics
Applicable over recommended operating range from T
A
= -40°C to +125°C, V
CC
= +2.7V to +5.5V
Symbol
V
CC1
V
CC2
I
CC1
I
CC2
I
SB1
I
SB2
I
IL
I
OL
V
IL(1)
V
IH(1)
V
OL1
V
OH1
Note:
Parameter
Supply Voltage
Supply Voltage
Supply Current
Supply Current
Standby Current
Standby Current
Input Leakage
Output Leakage
Input Low-voltage
Input High-voltage
Output Low-voltage
Output High-voltage
4.5
≤
V
CC
≤
5.5V
I
OL
= 3.0 mA
I
OH
= -1.6 mA
V
CC
- 0.8
V
CC
= 5.0V at 1 MHz, SO = Open, Read
V
CC
= 5.0V at 2 MHz,
SO = Open, Read, Write
V
CC
= 2.7V, CS = V
CC
V
CC
= 5.0V, CS = V
CC
V
IN
= 0V to V
CC
V
IN
= 0V to V
CC
-3.0
-3.0
-1.0
V
CC
x 0.7
Test Condition
Min
2.7
4.5
2.0
3.0
0.2
2.0
Typ
Max
5.5
5.5
3.0
5.0
2.0
5.0
3.0
3.0
V
CC
x 0.3
V
CC
+ 0.5
0.4
Units
V
V
mA
mA
µA
µA
µA
µA
V
V
V
V
1. V
IL
and V
IH
max are reference only and are not tested.
3
3262C–SEEPR–6/03
AC Characteristics
Applicable over recommended operating range from T
A
= -40°C to +125°C, V
CC
= As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
f
SCK
t
RI
t
FI
t
WH
t
WL
t
CS
t
CSS
t
CSH
t
SU
t
H
t
HD
t
CD
t
V
t
HO
t
LZ
t
HZ
t
DIS
t
WC
Endurance
(1)
Note:
Parameter
SCK Clock Frequency
Input Rise Time
Input Fall Time
SCK High Time
SCK Low Time
CS High Time
CS Setup Time
CS Hold Time
Data In Setup Time
Data In Hold Time
Hold Setup Time
Hold Hold Time
Output Valid
Output Hold Time
Hold to Output Low Z
Hold to Output High Z
Output Disable Time
Write Cycle Time
5.0V, 25°C, Page Mode
Voltage
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
4.5 - 5.5
2.7 - 5.5
100K
150
200
150
200
250
250
100
250
150
250
30
50
50
50
100
100
200
300
0
0
0
0
0
0
100
200
100
200
200
250
5
10
150
200
Min
0
0
Max
3.0
2.1
2
2
2
2
Units
MHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Write Cycles
1. This parameter is characterized and is not 100% tested. Contact Atmel for further information.
4
AT25128/256
3262C–SEEPR–6/03
AT25128/256
Serial Interface
Description
MASTER:
The device that generates the serial clock.
SLAVE:
Because the Serial Clock pin (SCK) is always an input, the AT25128/256
always operates as a slave.
TRANSMITTER/RECEIVER:
The AT25128/256 has separate pins designated for data
transmission (SO) and reception (SI).
MSB:
The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE:
After the device is selected with CS going low, the first byte will
be received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE:
If an invalid op-code is received, no data will be shifted into the
AT25128/256, and the serial output pin (SO) will remain in a high impedance state until
the falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT:
The AT25128/256 is selected when the CS pin is low. When the device
is not selected, data will not be accepted via the SI pin, and the serial output pin (SO)
will remain in a high impedance state.
HOLD:
The HOLD pin is used in conjunction with the CS pin to select the AT25128/256.
When the device is selected and a serial sequence is underway, HOLD can be used to
pause the serial communication with the master device without resetting the serial
sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To
resume serial communication, the HOLD pin is brought high while the SCK pin is low
(SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin
is in the high impedance state.
WRITE PROTECT:
The write protect pin (WP) will allow normal read/write operations
when held high. When the WP pin is brought low and WPEN bit is “1”, all write opera-
tions to the status register are inhibited. WP going low while CS is still low will interrupt a
write to the status register. If the internal write cycle has already been initiated, WP
going low will have no effect on any write operation to the status register. The WP pin
function is blocked when the WPEN bit in the status register is “0”. This will allow the
user to install the AT25128/256 in a system with the WP pin tied to ground and still be
able to write to the status register. All WP pin functions are enabled when the WPEN bit
is set to “1”.
5
3262C–SEEPR–6/03
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