Features
•
•
•
•
•
Extended Temperature Range for High Temperature up to 125°C
4-Kbyte ROM, 256
×
4-bit RAM
16 Bi-directional I/Os
Up to 7 External/Internal Interrupt Sources
Multifunction Timer/Counter with
– IR Remote Control Carrier Generator
– Bi-phase, Manchester and Pulse-width Modulator and Demodulator
– Phase Control Function
Programmable System Clock with Prescaler and Five Different Clock
Sources
Wide Supply-voltage Range (1.8 V to 6.5 V)
Very Low Sleep Current (< 1 µA)
Synchronous Serial Interface (2-wire, 3-wire)
Watchdog, POR and Brown-out Function
Voltage Monitoring Inclusive Lo_BAT Detect
Flash Controller ATAM893 Available (SSO20)
•
•
•
•
•
•
•
Low-current
Microcontroller
for Wireless
Communication
ATAR092-D
Description
The ATAR092-D is a member of Atmel’s family of 4-bit single-chip microcontrollers. It
offers the highest integration for IR and RF data communication, remote-control and
phase-control applications. The ATAR092-D is suitable as a transmitter as well as a
receiver. They contain ROM, RAM, parallel I/O ports, two 8-bit programmable multi-
function timer/counters with modulator and demodulator function, voltage supervisor,
interval timer with watchdog function and a sophisticated on-chip clock generation
w i t h ex t e r n a l c l o c k i n p u t , i n t e g r a t e d R C - , 3 2 -k H z c r y s t a l - a n d 4 - M H z
crystal-oscillators.
Figure 1.
Block Diagram
V
SS
V
DD
OSC1 OSC2
Brown-out protect.
RESET
Voltage monitor
External input
VMI
BP10
Port 1
BP13
BP20/NTE
Port 2
BP21
BP22
BP23
RC
Crystal
oscillators oscillators
External
clock input
UTCM
Timer 1
interval- and
watchdog timer
Timer 2
T2I
T2O
SD
Clock management
ROM
4 K x 8 bit
RAM
256 x 4 bit
8/12-bit timer
with modulator
SSI
MARC4
Data direction
Serial interface
Timer 3
8-bit
timer/counter
with modulator
and demodulator
SC
T3O
T3I
4-bit CPU core
I/O bus
Data direction +
alternate function
Port 4
Data direction +
interrupt control
Port 5
Data direction +
alternate function
Port 6
BP40
BP42
BP50
BP52
INT3
INT6
T2O
INT1
SC
BP43
BP41
BP53
BP51
VMI
INT3
INT6
INT1
T2I
SD
BP60
T3O
BP63
T3I
Rev. 4594C–4BMCU–12/04
Pin Configuration
Figure 2.
Pinning SSO20
VDD
BP40/INT3/SC
BP53/INT1
BP52/INT1
BP51/INT6
BP50/INT6
OSC1
OSC2
BP60/T3O
BP10
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VSS
BP43/INT3/SD
BP42/T2O
BP41/VMI/T2I
BP23
BP22
BP21
BP20/NTE
BP63/T3I
BP13
Pin Description
Name
VDD
VSS
BP10
BP13
BP20
BP21
BP22
BP23
BP40
BP41
BP42
BP43
BP50
BP51
BP52
BP53
BP60
BP63
OSC1
Type
–
–
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Function
Supply voltage
Circuit ground
Bi-directional I/O line of Port 1.0
Bi-directional I/O line of Port 1.3
Bi-directional I/O line of Port 2.0
Bi-directional I/O line of Port 2.1
Bi-directional I/O line of Port 2.2
Bi-directional I/O line of Port 2.3
Bi-directional I/O line of Port 4.0
Bi-directional I/O line of Port 4.1
Bi-directional I/O line of Port 4.2
Bi-directional I/O line of Port 4.3
Bi-directional I/O line of Port 5.0
Bi-directional I/O line of Port 5.1
Bi-directional I/O line of Port 5.2
Bi-directional I/O line of Port 5.3
Bi-directional I/O line of Port 6.0
Bi-directional I/O line of Port 6.3
Oscillator input
Alternate Function
–
–
–
–
NTE-test mode enable, see section “Master Reset”
–
–
–
SC-serial clock or INT3 external interrupt input
VMI voltage monitor input or T2I external clock
input Timer 2
T2O Timer 2 output
SD serial data I/O or INT3-external interrupt input
INT6 external interrupt input
INT6 external interrupt input
INT1 external interrupt input
INT1 external interrupt input
T3O Timer 3 output
T3I Timer 3 input
4-MHz crystal input or 32-kHz crystal input or
external clock input or external trimming resistor
input
4-MHz crystal output or 32-kHz crystal output or
external clock input
Pin No.
1
20
10
11
13
14
15
16
2
17
18
19
6
5
4
3
9
12
7
Reset State
NA
NA
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
OSC2
O
Oscillator output
8
NA
2
ATAR092-D
4594C–4BMCU–12/04
ATAR092-D
Introduction
The ATAR092-D is a member of Atmel’s family of 4-bit single-chip microcontrollers.
They contain ROM, RAM, parallel I/O ports, two 8-bit programmable multifunction
timer/counters, voltage supervision, interval timer with watchdog function, a sophisti-
cated on-chip clock generation with integrated RC-, 32-kHz crystal- and 4-MHz crystal
oscillators.
Table 1.
Available Variants of ATAxx9x
Version
Flash device
Production
Production
Type
ATAM893
ATAR092
ATAR892
ROM
4-Kbyte EEPROM
4-Kbyte mask ROM
4-Kbyte mask ROM
E2PROM Peripheral
64 byte
–
64 byte
Packages
SSO20
SSO20
SSO20
MARC4 Architecture
General Description
The MARC4 microcontroller consists of an advanced stack-based, 4-bit CPU core and
on-chip peripherals. The CPU is based on the HARVARD architecture with physically
separate program memory (ROM) and data memory (RAM). Three independent buses,
the instruction bus, the memory bus and the I/O bus, are used for parallel communica-
tion between ROM, RAM and peripherals. This enhances program execution speed by
allowing both instruction prefetching, and a simultaneous communication to the on-chip
peripheral circuitry. The extremely powerful integrated interrupt controller with associ-
ated eight prioritized interrupt levels supports fast and efficient processing of hardware
events. The MARC4 is designed for the high-level programming language qFORTH.
The core includes both an expression and a return stack. This architecture enables
high-level language programming without any loss of efficiency or code density.
Figure 3.
MARC4 Core
MARC4 CORE
Reset
Program
memory
PC
X
Y
SP
RP
RAM
256 x 4-bit
Reset
Clock
Instruction
bus
Instruction
decoder
Memory bus
TOS
CCR
System
clock
Sleep
Interrupt
controller
I/O bus
ALU
On-chip peripheral modules
3
4594C–4BMCU–12/04
Components of MARC4
Core
ROM
The core contains ROM, RAM, ALU, a program counter, RAM address registers, an
instruction decoder and an interrupt controller. The following sections describe each
functional block in more detail.
The program memory (ROM) is mask programmed with the customer application pro-
gram during the fabrication of the microcontroller. The 4 Kbytes ROM size is addressed
by a 12-bit wide program counter. An additional 1 Kbyte of ROM exists which is
reserved for quality control self-test software. The lowest user ROM address segment is
taken up by a 512-byte zero page which contains predefined start addresses for inter-
rupt service routines and special subroutines accessible with single byte instructions
(SCALL).
The corresponding memory map is shown in Figure 4. Look-up tables of constants can
also be held in ROM and are accessed via the MARC4’s built-in table instruction.
Figure 4.
ROM Map
FFFh
1F8h
1F0h
1E8h
1E0h
1E0h
1C0h
180h
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0
SCALL addresses
ROM
(4 K x 8 bit)
7FFh
Zero
page
140h
100h
0C0h
080h
1FFh
Zero page
000h
020h
018h
010h
008h
000h
040h
008h
000h
$RESET
$AUTOSLEEP
RAM
The ATAR092-D contain 256 x 4-bit wide static random access memory (RAM). It is
used for the expression stack, the return stack and data memory for variables and
arrays. The RAM is addressed by any of the four 8-bit wide RAM address registers SP,
RP, X and Y.
The 4-bit wide expression stack is addressed with the expression stack pointer (SP). All
arithmetic, I/O and memory reference operations take their operands from, and return
their results to the expression stack. The MARC4 performs the operations with the top of
stack items (TOS and TOS-1). The TOS register contains the top element of the expres-
sion stack and works in the same way as an accumulator. This stack is also used for
passing parameters between subroutines and as a scratch pad area for temporary stor-
age of data.
The 12-bit wide return stack is addressed by the return stack pointer (RP). It is used for
storing return addresses of subroutines, interrupt routines and for keeping loop index
counts. The return stack can also be used as a temporary storage area.
The MARC4 instruction set supports the exchange of data between the top elements of
the expression stack and the return stack. The two stacks within the RAM have a user
definable location and maximum depth.
Expression Stack
Return Stack
4
ATAR092-D
4594C–4BMCU–12/04
ATAR092-D
Figure 5.
RAM Map
RAM
(256 x 4-bit)
Autosleep
FCh
FFh
Global
variables
Expression stack
3
0
TOS
TOS-1
TOS-2
4-bit
Expression
stack
Return
stack
SP
RAM Address Register:
X
Y
Return stack
11
0
RP
SP
TOS-1
RP
04h
00h
07h
03h
Global
v
variables
12-bit
Registers
The MARC4 controller has seven programmable registers and one condition code regis-
ter. They are shown in the following programming model (Figure 6).
The program counter is a 12-bit register which contains the address of the next instruc-
tion to be fetched from ROM. Instructions currently being executed are decoded in the
instruction decoder to determine the internal micro-operations. For linear code (no calls
or branches) the program counter is incremented with every instruction cycle. If a
branch-, call-, return-instruction or an interrupt is executed, the program counter is
loaded with a new address. The program counter is also used with the table instruction
to fetch 8-bit wide ROM constants.
Figure 6.
Programming Model
11
PC
7
RP
7
SP
7
X
7
Y
3
TOS
3
C
--
B
0
I
0
Top of stack register
Condition code register
Interrupt enable
Branch
Reserved
Carry/borrow
0
RAM address register (Y)
0
RAM address register (X)
0
0
0
0
Expression stack pointer
Return stack pointer
0
Program counter
Program Counter (PC)
CCR
5
4594C–4BMCU–12/04
Wireless Connectivity
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