TS80C52ZZZ-VJB datasheet, PDF - EEWORLD Datasheet

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TS80C52ZZZ-VJB: DescriptionMicrocontroller, 8-Bit, MROM, 40MHz, CMOS, PQCC44, PLASTIC, LCC-44; CategoryThe embedded processor and controller Microcontrollers and processors; File Size835KB，54 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

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TS80C52ZZZ-VJB Overview

Microcontroller, 8-Bit, MROM, 40MHz, CMOS, PQCC44, PLASTIC, LCC-44

TS80C52ZZZ-VJB Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Atmel (Microchip)
Parts packaging code	LCC
package instruction	QCCJ,
Contacts	44
Reach Compliance Code	compliant
ECCN code	3A991.A.2
Has ADC	NO
Address bus width	16
bit size	8
maximum clock frequency	40 MHz
DAC channel	NO
DMA channel	NO
External data bus width	8
JESD-30 code	S-PQCC-J44
JESD-609 code	e3
length	16.55 mm
Humidity sensitivity level	2
Number of I/O lines	32
Number of terminals	44
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	NO
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	245
Certification status	Not Qualified
ROM programmability	MROM
Maximum seat height	4.57 mm
speed	40 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	16.55 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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Features

•

80C52 Compatible

– 8051 Pin and Instruction Compatible

– Four 8-bit I/O Ports

– Three 16-bit Timer/Counters

– 256 Bytes Scratchpad RAM

High-speed Architecture

40 MHz at 5V, 30 MHz at 3V

X2 Speed Improvement Capability (6 Clocks/Machine Cycle)

– 30 MHz at 5V, 20 MHz at 3V (Equivalent to 60 MHz at 5V, 40 MHz at 3V)

Dual Data Pointer

On-chip ROM/EPROM (8Kbytes)

Programmable Clock Out and Up/Down Timer/Counter 2

Asynchronous Port Reset

Interrupt Structure with

– 6 Interrupt Sources

– 4 Level Priority Interrupt System

Full Duplex Enhanced UART

– Framing Error Detection

– Automatic Address Recognition

Low EMI (Inhibit ALE)

Power Control Modes

– Idle Mode

– Power-down Mode

– Power-off Flag

Once Mode (On-chip Emulation)

Power Supply: 4.5 - 5.5V, 2.7 - 5.5V

Temperature Ranges: Commercial (0 to 70

C) and Industrial (-40 to 85

Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44 (13.9 footprint)

•

8-bit

Microcontroller

8 Kbytes

ROM/OTP,

ROMless

TS80C32X2

TS87C52X2

TS80C52X2

•

Description

TS80C52X2 is high performance CMOS ROM, OTP, EPROM and ROMless versions

of the 80C51 CMOS single chip 8-bit microcontroller.

The TS80C52X2 retains all features of the 80C51 with extended ROM/EPROM

capacity (8 Kbytes), 256 bytes of internal RAM, a 6-source, 4-level interrupt system,

an on-chip oscilator and three timer/counters.

In addition, the TS80C52X2 has a dual data pointer, a more versatile serial channel

that facilitates multiprocessor communication (EUART) and an X2 speed improve-

ment mechanism.

The fully static design of the TS80C52X2 allows to reduce system power consumption

by bringing the clock frequency down to any value, even DC, without loss of data.

The TS80C52X2 has 2 software-selectable modes of reduced activity for further

reduction in power consumption. In the idle mode the CPU is frozen while the timers,

the serial port and the interrupt system are still operating. In the power-down mode the

RAM is saved and all other functions are inoperative.

Rev. 4184E–8051–09/02

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