PRELIMINARY
TECHNOLOGY, INC.
MT28F002
256K x 8 FLASH MEMORY
FLASH MEMORY
FEATURES
• Five erase blocks:
- 16KB boot block (protected)
- Two 8KB parameter blocks
- Two main memory blocks
• 5V
±10%
V
CC
; 12V
±5%
V
PP
• Address access times: 60ns, 80ns, 100ns
• Industry-standard pinouts
• Inputs and outputs are fully TTL-compatible
• Automated write and erase algorithm
256K x 8
5V/12V, BOOT BLOCK
PIN ASSIGNMENT (Top View)
40-Pin TSOP Type I
A16
A15
A14
A13
A12
A11
A9
A8
WE
RST
Vpp
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
Vss
NC
NC
A10
DQ7
DQ6
DQ5
DQ4
Vcc
Vcc
NC
DQ3
DQ2
DQ1
DQ0
OE
Vss
CE
A0
OPTIONS
• Timing
60ns
80ns
100ns
• Boot-Block Starting Address
Top (3FFFFH)
Bottom (00000H)
MARKING
- 6
- 8
-10
T
B
• Packages
Plastic 40L TSOP Type 1 (10 x 20mm)
VG
• Part Number Example: MT28F002VG-8 T
GENERAL DESCRIPTION
The MT28F002 is a nonvolatile, electrically block-
erasable (Flash), programmable read-only memory con-
taining 2,097,152 bits organized as 262,144 words by 8 bits.
It is fabricated with Micron’s advanced CMOS floating-gate
process.
The MT28F002 is organized into five separately erasable
blocks. To ensure that critical firmware is protected from
accidental erasure or overwrite, the MT28F002 features a
hardware-protected boot block. Writing or erasing the boot
MT28F002
F02.pm5 – Rev. 6/95
block requires applying a super-voltage to the RS
/
T pin in
? /
addition to executing the normal write or erase sequences.
This block may be used to store code implemented in low-
level system recovery. The remaining blocks vary in density,
and are written-to and erased with no additional security
measures.
The byte address is issued to read the memory array with
?
C
/
E and O
/
E LOW and
?
W
/
E HIGH. Valid data is output until
?
the next address is issued or
?
C
/
E or
?
O
/
E go HIGH.
1
Micron Quantum Devices, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Quantum Devices, Inc.
PRELIMINARY
TECHNOLOGY, INC.
MT28F002
256K x 8 FLASH MEMORY
PIN DESCRIPTIONS
TSOP PIN
NUMBERS
9
SYMBOL
?
W
/
E
TYPE
Input
DESCRIPTION
Write Enable: Determines if a given cycle is a write cycle. If
?
W
/
E = LOW,
the cycle is either a WRITE to the Command Execution Logic (CEL) or to
the memory array.
Chip Enable: Activates the device when LOW. When
?
C
/
E is HIGH, the
device is disabled and goes into standby power mode.
Reset: Clears the status register, sets the Internal State Machine (ISM) to
the array read mode, and places the device in standby mode when LOW.
All inputs, including
?
C
/
E, are “don’t care” and all outputs are High-Z. Also
used to unlock boot block when brought to V
HH
(boot-block unlock
voltage; 12V). Must be held HIGH during all other modes of operation.
Output Enable: Enables data output buffers when LOW. When
?
O
/
E is
HIGH, the output buffers are disabled.
Address Inputs: Selects a unique byte out of the 262,144 available.
22
10
?
C
/
E
?
R
/
S
/
T
Input
Input
24
21, 20, 19, 18,
17, 16, 15, 14,
8, 7, 36, 6, 5,
4, 3, 2, 1, 40,
25, 26, 27, 28,
32, 33, 34, 35
12, 13, 29, 37,
38
11
?
O
/
E
A0-A17
Input
Input
DQ0-DQ7
Input/
Output
-
Supply
Data I/O: Data output pins during any read operation, or data
input pins during a WRITE. Used to input commands to the CEL for
a command input.
No Connect: These pins may be driven or left unconnected.
Write/Erase Supply Voltage: Write/Erase Supply Voltage: During a
WRITE or ERASE CONFIRM, V
PP
=V
PPH
(12V). V
PP
= “don’t care” during
all other operations.
Power Supply: +5V
±10%
Ground
NC
V
PP
30, 31
23, 39
V
CC
V
SS
Supply
Supply
MT28F002
F02.pm5 – Rev. 6/95
3
Micron Quantum Devices, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Quantum Devices, Inc.
PRELIMINARY
TECHNOLOGY, INC.
MT28F002
256K x 8 FLASH MEMORY
FUNCTIONAL DESCRIPTION
The MT28F002 Flash memory incorporates a number of
features to make it ideally suited for system firmware.
The memory array is segmented into individual erase
blocks. Each block may be erased without affecting data
stored in other blocks. These memory blocks are read,
written and erased by issuing commands to the Command
Execution Logic (CEL). The CEL controls the operation of
the Internal State Machine (ISM), which completely con-
trols all write, block erase, and verify operations. The ISM
protects each memory location from over-erasure and
optimizes each memory location for maximum data reten-
tion. In addition, the ISM greatly simplifies the control
necessary for writing the device in-system or in an external
programmer.
The Functional Description provides detailed informa-
tion on the operation of the MT28F002, and is organized into
these sections:
•
•
•
•
•
•
•
•
•
•
•
Overview
Memory Architecture
Output (Read) Operations
Input Operations
Command Set
ISM Status Register
Command Execution
Error Handling
Write/Erase Cycle Endurance
Power Usage
Powerup
HARDWARE-PROTECTED BOOT BLOCK
This block of the memory array can be erased or written
only when the
?
R
/
S
/
T pin is taken to V
HH
. Designing a system
so that the processor or control logic is unable to apply 12V
to this pin will ensure data integrity in this memory block.
This provides additional security for the core firmware
during in-system firmware updates, should an uninten-
tional power fluctuation or system reset occur. The
MT28F002 is available in two versions; the MT28F002T
addresses the boot block starting from 3FFFFH, and the
MT28F002B addresses the boot block starting from 00000H.
INTERNAL STATE MACHINE (ISM)
Block erase and write timing are simplified by using an
ISM to control all erase and write algorithms in the memory
array. The ISM ensures protection against over-erasure and
optimizes write margin to each cell.
During write operations the ISM automatically incre-
ments and monitors write attempts, verifies write margin
on each memory cell, and updates the ISM status register.
When block erase is performed, the ISM automatically
overwrites the entire addressed block (eliminates over-
erasure), increments and monitors erase attempts, and sets
bits in the ISM status register.
ISM STATUS REGISTER
The ISM status register allows an external processor to
monitor the status of the ISM during write and erase opera-
tions. Two bits of the 8-bit status register are set and cleared
entirely by the ISM. These bits indicate whether the ISM is
busy with an erase or write task and when an erase has been
suspended. Additional error information is set in three
other bits: valid V
PP
voltage, write error and erase error.
COMMAND EXECUTION LOGIC (CEL)
The CEL receives and interprets commands to the device.
These commands control the operation of the ISM and the
read path (i.e. memory array, ID register, or status register).
Commands may be issued to the CEL while the ISM is
active. However, there are restrictions on what commands
are allowed in this condition. See the Command Execution
section for more detail.
OVERVIEW
FIVE INDEPENDENTLY ERASABLE MEMORY
BLOCKS
The MT28F002 is organized into five independently eras-
able memory blocks that allow portions of the memory to be
erased without affecting the rest of the memory data. A
special boot block is hardware-protected against inadvert-
ent erasure or writes by a super-voltage pin. The voltage on
this pin is required in addition to the 12V on the V
PP
pin. The
remaining blocks require only the 12V V
PP
to be present in
order to be changed.
MT28F002
F02.pm5 – Rev. 6/95
5
Micron Quantum Devices, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Quantum Devices, Inc.
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