U2752M
Digital I/Q-Generator Chip for DAB
Description
The U2752M is an integrated circuit in CMOS
technology for splitting a digital DAB signal into its
quadrature components. The device is designed for DAB
(ETS 300 401) applications.
Electrostatic sensitive device.
Observe precautions for handling.
Features
D
U2752M splits a digital DAB input signal into its
D
D
D
quadrature components
Quadrature matching: 0 dB in magnitude,
≤
1.6° in phase
Clock frequency: 4.096 MHz
Input signal
– Center frequency: 3.072 MHz
–
Bandwidth: 1.536 MHz
–
Data format:
8 bit, 4.096 MHz in 2’s complement representation
D
Output signal
– Select pin for baseband or 1.024-MHz center
frequency
–
I-, Q- components in time multiplex
–
Data format:
8 bit, 4.096 MHz in 2’s complement representation
Block Diagram
2
8
DATA_IN
AP–I
IQDATA
7
MUX
2
AP–Q
DATA_RI
RESET
CLOCK
96 12265
VDD VSS
MIX_OFF
Figure 1. Block diagram
Ordering Information
Extended Type Number
U2752M-AFL
U2752M-AFLG3
Package
SO24
SO24
Remarks
Taping according to IEC-286-3
Rev. A1, 29-Jun-98
1 (6)
Preliminary Information
U2752M
Pin Description
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BUFINMOS
BUFINMOS
BUFINMOS
BUFINMOS
BUFINMOS
BUFINMOS
BUFINMOS
BUFINMOS
BUFTGMOS
BU2OUT
BU2OUT
BU2OUT
BU2OUT
BU2OUT
BU2OUT
BU2OUT
BU2OUT
BU2OUT
MIX_OFF 1
RESET
VSS
DATA_IN0
DATA_IN1
DATA_IN2
DATA_IN3
DATA_IN4
DATA_IN5
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
15
14
13
96 12266
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Signal
MIX_OFF
RESET
VSS
DATA_IN0
DATA_IN1
DATA_IN2
DATA_IN3
DATA_IN4
DATA_IN5
DATA_IN6
DATA_IN7
VSS
CLOCK
DATA_RI
VDD
IQDATA7
IQDATA6
IQDATA5
IQDATA4
IQDATA3
IQDATA2
IQDATA1
IQDATA0
VDD
Description
Low: I/Q in baseband representation, High. I/Q in IF representation
Reset signal, high active
Ground
Data input (LSB)
Data input
Data input
Data input
Data input
Data input
Data input
Data input (MSB)
Ground
System clock 4.096 MHz
Internal data_ri signal
Power supply
Data_output, I and Q multiplex (MSB)
Data_output, I and Q multiplex
Data_output, I and Q multiplex
Data_output, I and Q multiplex
Data_output, I and Q multiplex
Data_output, I and Q multiplex
Data_output, I and Q multiplex
Data_output, I and Q multiplex (LSB)
Power supply
PAD Type
BUFINCDN
BUFINCDN
VDD
IQDATA0
IQDATA1
IQDATA2
IQDATA3
IQDATA4
IQDATA5
IQDATA6
IQDATA7
VDD
DATA_RI
CLOCK
Functional Description
The U2752M generates the in-phase and quadrature
components of the DAB input signal with a quadrature
matching of 0 dB in magnitude and a maximum value of
1.6° in phase. The clock of the device is 4.096 MHz.
The data format of the input signal DATA_IN is 8 bits,
sampled with 4.096 MHz in 2’s complement represen-
tation. Its center frequency is 3.072 MHz with a
bandwidth of 1536 MHz. The U2752M uses decimation
and common filter techniques to generate the quadrature
components.
The output interface consists of the split signal IQDATA
with a data format of 8 bits, 4.096 MHz in 2’s comple-
ment representation. The in-phase (I) and quadrature (Q)
components are represented in time division multiplex
format with a selection signal DATA_RI of 4.096 MHz.
The output representation in baseband or 1.024-MHz
center frequency is selected by the MIX_OFF signal. For
utilization together with TEMIC’s U2752M device, the
baseband representation (MIX_OFF = ‘0’) must be
selected.
DATA_IN6 10
DATA_IN7 11
VSS
12
Figure 2. Pinning
2 (6)
Rev. A1, 29-Jun-98
Preliminary Information
U2752M
Absolute Maximum Ratings
Parameters
DC supply voltage
Input / output voltage
Storage temperature
Symbol
V
DD
V
in
/V
out
T
stg
Min.
–0.5
–0.5
–65
Typ.
Max.
+7
V
DD
+ 0.5
+150
Unit
V
V
°C
Operating Range
Parameters
DC supply voltage
Input / output voltage
Ambient temperature
Power dissipation (static)
Power dissipation (dynamic)
Symbol
V
DD
V
in
/V
out
T
amb
P
stat
P
dyn
Min.
4.5
0
–40
Typ.
Max.
5.5
V
DD
+85
Unit
V
V
°C
mW
mW
0.25
15
Thermal Resistance
Parameters
Junction ambient SO24
Symbol
R
thJA
Value
80
Unit
K/W
Electrical Characteristics
Test conditions: V
DD
= 5 V, T
amb
= 25°C
Parameters
Input HIGH voltage
Input LOW voltage
Positive threshold
Negative threshold
Input leakage
Test Conditions / Pins
Pins 1, 2, 4 to 11
Pins 1, 2, 4 to 11
Pin 13
V
IN
= V
DD
or V
SS
V
IN
= V
DD
Pins 1, 2, 4 to 11 and 13
I
OH
= +6.4 mA
Pins 14, 16 to 23
I
OH
= –6.4 mA
Pins 14, 16 to 23
Symbol
V
IH
V
IL
V
T+
V
T–
I
L
Min.
3.5
1.61
2.47
±1
+40
2.4
0.4
Typ.
Max.
1.5
2.60
3.52
±5
+100
Unit
V
V
V
V
µA
µA
V
V
Output HIGH voltage
Output LOW voltage
V
OH
V
OL
Rev. A1, 29-Jun-98
3 (6)
Preliminary Information
U2752M
Input Interface Description
RESET
CLOCK
Internal RI
selection signal
DATA_IN
R
tsu_din
Figure 3. Input interface signals (tsu_din
≥
10 ns)
I
R
I
96 12267
Phase deviation from 90 degree
For verification purposes, it can be helpful to know how
the U2752M selects the input samples for real and imagi-
nary data processing.
The U2752M generates an internal real and imaginary
selection signal, which depends on the first recognized
rising CLOCK edge as shown in figure 3. Due to this
selection signal, the data input DATA_IN will be used for
the real or imaginary process path of the IC. The setup
time of DATA_IN tsu_din must be
≥
10 ns.
100
80
60
40
20
0
–20
–40
–60
–80
–100
0
96 12047
max. phase mismatch = 1.6 deg
max. amplitude mismatch = 0 dB
Results
The phase deviation from 90° of the I- and Q- parts over
the normalized frequency is shown in figure 4.
The DAB-relevant frequency range is from 1/8 to 7/8 on
the normalized frequency axis.
For the DAB frequency range, the maximum phase mis-
match is 1.6° and the amplitude mismatch is 0 dB.
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Normalized frequency
Figure 4. Phase deviation of the I- and Q–parts
4 (6)
Rev. A1, 29-Jun-98
Preliminary Information
U2752M
Package Information
Package SO24
Dimensions in mm
15.55
15.30
9.15
8.65
7.5
7.3
2.35
0.25
0.10
13.97
24
13
0.25
10.50
10.20
0.4
1.27
technical drawings
according to DIN
specifications
13037
1
12
Rev. A1, 29-Jun-98
5 (6)
Preliminary Information
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