AM29F004BT-90JI datasheet, PDF

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AM29F004BT-90JI: DescriptionFlash, 512KX8, 90ns, PQCC32, PLASTIC, MO-052AE, LCC-32; Categorystorage storage; File Size356KB，38 Pages; ManufacturerAMD; Websitehttp://www.amd.com

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AM29F004BT-90JI Overview

Flash, 512KX8, 90ns, PQCC32, PLASTIC, MO-052AE, LCC-32

AM29F004BT-90JI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	AMD
Parts packaging code	LCC
package instruction	QCCJ, LDCC32,.5X.6
Contacts	32
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum access time	90 ns
Other features	MINIMUM 1000K WRITE CYCLES; 20 YEAR DATA RETENTION
startup block	TOP
command user interface	YES
Data polling	YES
Data retention time - minimum	20
JESD-30 code	R-PQCC-J32
JESD-609 code	e0
length	13.97 mm
memory density	4194304 bit
Memory IC Type	FLASH
memory width	8
Number of functions	1
Number of departments/size	1,2,1,7
Number of terminals	32
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX8
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC32,.5X.6
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
power supply	5 V
Programming voltage	5 V
Certification status	Not Qualified
Maximum seat height	3.556 mm
Department size	16K,8K,32K,64K
Maximum standby current	0.000005 A
Maximum slew rate	0.04 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
switch bit	YES
type	NOR TYPE
width	11.43 mm

AM29F004BT-90JI Preview

Am29F004B

Data Sheet

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-

inally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appropriate,

and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order

these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Publication Number

22286

Revision

Amendment

Issue Date

November 29, 2000

Am29F004B

4 Megabit (512 K x 8-Bit)

CMOS 5.0 Volt-only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

5.0 Volt single power supply operation

— Minimizes system-level power requirements

High performance

— Access times as fast as 55 ns

Manufactured on 0.32 µm process technology

Ultra low power consumption (typical values at

5 MHz)

— 20 mA typical active read current

— 30 mA typical program/erase current

— 1 µA typical standby mode current

Flexible sector architecture

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

seven 64 Kbyte sectors

— Supports full chip erase

— Sector Protection features:

A hardware method of locking a sector to

prevent any program or erase operations within

that sector

Sectors can be locked in-system or via

programming equipment

Temporary Sector Unprotect feature allows code

changes in previously locked sectors

Top or bottom boot block configurations available

Minimum 1,000,000 write cycle guarantee per

sector

Package option

— 32-pin PLCC

Compatible with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

Embedded Algorithms

— Embedded Erase algorithm automatically

preprograms and erases the entire chip or any

combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specified addresses

Erase Suspend/Erase Resume

— Suspends an erase operation to read data from,

or program data to, a sector that is not being

erased, then resumes the erase operation

Data# Polling and toggle bits

— Provides a software method of detecting

program or erase operation completion

20-year data retention at 125°C

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data

Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.

Publication#

22286

Rev:

Amendment/0

Issue Date:

November 29, 2000

GENERAL DESCRIPTION

The Am29F004B is a 4 Mbit, 5.0 volt-only Flash

memory device organized as 524,288 bytes. The data

appears on DQ0–DQ7. The device is offered in a 32-

pin PLCC package. This device is designed to be pro-

grammed in-system with the standard system 5.0 volt

supply. A 12.0 volt V

is not required for program or

erase operations. The device can also be programmed in

standard EPROM programmers.

The device offers access times of 55, 70, 90, and 120 ns,

allowing high speed microprocessors to operate

without wait states. To eliminate bus contention each

device has separate chip enable (CE#), write enable

(WE#) and output enable (OE#) controls.

Each device requires only a

single 5.0 volt power

supply

for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

The Am29F004B is entirely command set compatible

with the

JEDEC single-power-supply Flash stan-

dard.

Commands are written to the command register

using standard microprocessor write timing. Register

contents serve as inputs to an internal state-machine

that controls the erase and programming circuitry.

Write cycles also internally latch addresses and data

needed for the programming and erase operations.

Reading data out of the device is similar to reading

from other Flash or EPROM devices.

Device programming occurs by executing the program

command sequence. This initiates the

Embedded

Program

algorithm-an internal algorithm that automat-

ically times the program pulse widths and verifies

proper cell margin.

Device erasure occurs by executing the erase

command sequence. This initiates the

Embedded

Erase

algorithm–an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by reading the DQ7 (Data#

Polling), or DQ6 (toggle)

status bits.

After a program

or erase cycle has been completed, the device is ready

to read array data or accept another command.

The

sector erase architecture

allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection

measures include a low

detector that automatically inhibits write operations

during power transitions. The

hardware sector

protection

feature disables both program and erase operations in

any combination of sectors of memory. This can be

achieved in-system or via programming equipment.

The

Erase Suspend

feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The device offers a

standby mode

as a power-saving

feature. Once the system places the device into the

standby mode power consumption is greatly reduced.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within a

sector simultaneously via Fowler-Nordheim tunnelling.

The data is programmed using hot electron injection.

Am29F004B

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 8

Table 1. Am29F004B Device Bus Operations ..................................8

DQ5: Exceeded Timing Limits ................................................ 20

DQ3: Sector Erase Timer ....................................................... 21

Figure 6. Toggle Bit Algorithm ........................................................ 21

Table 6. Write Operation Status ..................................................... 22

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 23

Figure 7. Maximum Negative Overshoot Waveform ...................... 23

Figure 8. Maximum Positive Overshoot Waveform ........................ 23

Requirements for Reading Array Data ..................................... 8

Writing Commands/Command Sequences .............................. 8

Program and Erase Operation Status ...................................... 8

Standby Mode .......................................................................... 8

Output Disable Mode ................................................................ 9

Table 2. Am29F004B Top Boot Block Sector Addresses .................9

Table 3. Am29F004B Bottom Boot Block Sector Addresses ............9

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 23

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24

TTL/NMOS Compatible .......................................................... 24

CMOS Compatible .................................................................. 25

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 9. Test Setup ....................................................................... 26

Table 7. Test Specifications ........................................................... 26

Autoselect Mode ..................................................................... 10

Table 4. Am29F004B Autoselect Codes (High Voltage Method) ....10

Key to Switching Waveforms. . . . . . . . . . . . . . . . 26

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27

Read Operations .................................................................... 27

Figure 10. Read Operations Timings ............................................. 27

Sector Protection/Unprotection ............................................... 10

Figure 1. In-System Sector Protect/Sector Unprotect Algorithms ...11

Erase/Program Operations ..................................................... 28

Figure 11. Program Operation Timings .......................................... 29

Figure 12. Chip/Sector Erase Operation Timings .......................... 29

Figure 13. Data# Polling Timings (During Embedded Algorithms) . 30

Figure 14. Toggle Bit Timings (During Embedded Algorithms) ...... 30

Figure 15. DQ2 vs. DQ6 ................................................................. 30

Figure 16. Sector Unlock Sequence Timing Diagram .................... 31

Figure 17. Sector Relock Timing Diagram ..................................... 31

Figure 18. Sector Protect/Unprotect Timing Diagram .................... 32

Temporary Sector Unprotect .................................................. 12

Figure 2. Temporary Sector Unprotect Operation ...........................12

Hardware Data Protection ...................................................... 13

Low V

Write Inhibit ......................................................................13

Write Pulse “Glitch” Protection ........................................................13

Logical Inhibit ..................................................................................13

Power-Up Write Inhibit ....................................................................13

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 14

Reading Array Data ................................................................ 14

Reset Command ..................................................................... 14

Autoselect Command Sequence ............................................ 14

Byte Program Command Sequence ....................................... 14

Figure 3. Program Operation ..........................................................15

Alternate CE# Controlled Erase/Program Operations ............ 33

Figure 19. Alternate CE# Controlled Write Operation Timings ...... 34

Chip Erase Command Sequence ........................................... 15

Sector Erase Command Sequence ........................................ 15

Figure 4. Erase Operation ...............................................................16

Erase Suspend/Erase Resume Commands ........................... 17

Command Definitions ............................................................. 18

Table 5. Am29F004B Command Definitions ...................................18

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 19

DQ7: Data# Polling ................................................................. 19

Figure 5. Data# Polling Algorithm ...................................................19

DQ6: Toggle Bit I .................................................................... 20

DQ2: Toggle Bit II ................................................................... 20

Reading Toggle Bits DQ6/DQ2 .............................................. 20

Erase and Programming Performance . . . . . . . 35

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 35

PLCC Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 35

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 36

PL 032—32-Pin Plastic Leaded Chip Carrier ......................... 36

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 37

Revision A (January 1999) ..................................................... 37

Revision B (March 10, 1999) .................................................. 37

Revision B+1 (March 18, 1999) .............................................. 37

Revision B+2 (May 14, 1999) ................................................. 37

Revision B+3 (July 12, 1999) .................................................. 37

Revision C (November 12, 1999) ........................................... 37

Revision D (February 22, 2000) .............................................. 37

Revision E (November 29, 2000) ............................................ 37

Am29F004B

PRODUCT SELECTOR GUIDE

Family Part Number

Speed Option

= 5.0 V ± 5%

= 5.0 V ± 10%

Max access time, ns (t

ACC

)

Max CE# access time, ns (t

)

Max OE# access time, ns (t

)

-55

-70

-90

-120

120

Am29F004B

Note:

See “AC Characteristics” for full specifications.

BLOCK DIAGRAM

DQ0

–

DQ7

Erase Voltage

Generator

Input/Output

Buffers

Sector Switches

WE#

State

Control

Command

PGM Voltage

Generator

Chip Enable

Output Enable

Logic

STB

Data

Latch

CE#

OE#

STB

Detector

Timer

Address Latch

Y-Decoder

Y-Gating

X-Decoder

Cell Matrix

A0–A18

Am29F004B

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