HY57V2571620TC-10P datasheet, PDF

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HY57V2571620TC-10P: DescriptionSynchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54; Categorystorage storage; File Size129KB，11 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

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HY57V2571620TC-10P Overview

Synchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54

HY57V2571620TC-10P Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SK Hynix
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP54,.46,32
Contacts	54
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	6 ns
Maximum clock frequency (fCLK)	100 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PDSO-G54
JESD-609 code	e0
length	22.22 mm
memory density	268435456 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	54
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX16
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP54,.46,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	1.2 mm
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.001 A
Maximum slew rate	0.18 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10.16 mm

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HY57V2571620

4Banks x 4M x 16Bit Synchronous DRAM

Preliminary

DESCRIPTION

The Hyundai HY57V2571620 is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory

applications which require large memory density and high bandwidth. HY57V2571620 is organized as 4banks of

4,196,304x16.

HY57V2571620 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-

puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very

high bandwidth. All input and output voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 1,2, or 3), the number of consecutive read or

write cycles initiated by a single control command (Burst length of 1,2,4,8, or full page), and the burst count

sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate

command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined

design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3V

0.3V power supply

All device pins are compatible with LVTTL interface

JEDEC standard 400mil 54pin TSOP-II with 0.8mm

of pin pitch

All inputs and outputs referenced to positive edge of

system clock

Data mask function by DQM

Internal four banks operation

•

Auto refresh and self refresh

8192 refresh cycles / 64ms

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 and Full Page for Sequential Burst

•

- 1, 2, 4 and 8 for Interleave Burst

Programmable CAS Latency ; 2, 3 Clocks

•

ORDERING INFORMATION

Part No.

HY57V2571620TC-8

HY57V2571620TC-10P

HY57V2571620TC-10S

HY57V2571620TC-10

HY57V2571620LTC-8

HY57V2571620LTC-10P

HY57V2571620LTC-10S

HY57V2571620LTC-10

Clock Frequency

125MHz

100MHz

Power

Organization

Interface

Package

Normal

100MHz

125MHz

100MHz

Low Power

100MHz

4Banks x 4Mbits

x16

LVTTL

400mil 54pin TSOP II

This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Revision 0.1 / Jul.98

HY57V2571620TC-10P Related Products

	HY57V2571620TC-10P	HY57V2571620LTC-10P	HY57V2571620TC-8	HY57V2571620LTC-8	HY57V2571620TC-10S	HY57V2571620TC-10	HY57V2571620LTC-10	HY57V2571620LTC-10S
Description	Synchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54	Synchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54	Synchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54	Synchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54	Synchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54	Synchronous DRAM, 16MX16, 8ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54	Synchronous DRAM, 16MX16, 8ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54	Synchronous DRAM, 16MX16, 6ns, CMOS, PDSO54, 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Parts packaging code	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2
package instruction	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32	TSOP2, TSOP54,.46,32
Contacts	54	54	54	54	54	54	54	54
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	6 ns	6 ns	6 ns	6 ns	6 ns	8 ns	8 ns	6 ns
Maximum clock frequency (fCLK)	100 MHz	100 MHz	125 MHz	125 MHz	100 MHz	100 MHz	100 MHz	100 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
interleaved burst length	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8
JESD-30 code	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54
JESD-609 code	e0	e0	e0	e0	e0	e0	e0	e0
length	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm
memory density	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bit
Memory IC Type	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
memory width	16	16	16	16	16	16	16	16
Number of functions	1	1	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1	1	1
Number of terminals	54	54	54	54	54	54	54	54
word count	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words	16777216 words
character code	16000000	16000000	16000000	16000000	16000000	16000000	16000000	16000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	16MX16	16MX16	16MX16	16MX16	16MX16	16MX16	16MX16	16MX16
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2
Encapsulate equivalent code	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32	TSOP54,.46,32
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	8192	8192	8192	8192	8192	8192	8192	8192
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
Continuous burst length	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP
Maximum standby current	0.001 A	0.001 A	0.001 A	0.001 A	0.001 A	0.001 A	0.001 A	0.001 A
Maximum slew rate	0.18 mA	0.18 mA	0.18 mA	0.18 mA	0.18 mA	0.16 mA	0.16 mA	0.18 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm
Maker	SK Hynix	SK Hynix	SK Hynix	-	SK Hynix	SK Hynix	SK Hynix	SK Hynix

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